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LPC47M112 Datasheet, PDF (180/208 Pages) SMSC Corporation – ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
Enhanced Super I/O Controller with LPC Interface
Datasheet
PARAMETER
SYMBOL MIN TYP
Backdrive
IIL
Protect/ChiProtect
(All pins excluding LAD[3:0],
nLDRQ, nLPCPD, nLFRAME)
5V Tolerant Pins
IIL
(All pins excluding LAD[3:0],
nLDRQ, nLPCPD, nLFRAME)
Inputs and Outputs in High
Impedance State
LPC Bus Pins
IIL
(LAD[3:0], nLDRQ, nLPCPD,
nLFRAME)
VCC Supply Current Active
ICCI
Trickle Supply Voltage
VTR Supply Current Active
VTR
VCC
min
-.5V
ITRI
0.253,5
Reference Voltage
VREF Supply Current Active
VREF
IRFI
MAX
± 10
± 10
± 10
153
VCC
max
103,4
5.5
13
UNITS
COMMENTS
µA VCC = 0V
VIN = 5.5V Max
µA VCC = 3.3V
VIN = 5.5V Max
µA VCC = 0V and
VCC = 3.3V
VIN = 3.6V Max
mA All outputs open, all
inputs at a fixed
state (i.e., 0V or
3.3V).
V VCC must not be
greater than .5V
above VTR
mA All outputs open, all
inputs at a fixed
state (i.e., 0V or
3.3V).
V VREF can be either
3.3V (nominal) or
5V (nominal)
mA All outputs open, all
inputs at a fixed
state (i.e., 0V or
3.3V).
Note 1: All output leakage’s are measured with all pins in high impedance.
Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance
state.
Note 3: Contact SMSC for the latest values.
Note 4: Max ITRI with VCC = 3.3V (nominal) and CIR ‘on’ is 10 mA.
Note 5: Min ITRI with VCC = 0 and CIR ‘off’ is 250 µA.
CAPACITANCE TA = 25°C; fc = 1MHz; VCC = 3.3V ±10%
LIMITS
PARAMETER
SYMBOL MIN TYP
Clock Input Capacitance
CIN
Input Capacitance
CIN
Output Capacitance
COUT
MAX
20
10
20
UNIT
pF
pF
pF
TEST CONDITION
All pins except pin
under test tied to
AC ground
SMSC DS – LPC47M112
Page 180
Rev. 02/02/2005