COM20020_00 Datasheet, PDF (54/82 Pages) SMSC Corporation – Universal Local Area Network Controller with 2K x 8 On-Board RAM

In the Command Chaining Mode, at any time after
the first command is issued, the processor can
issue a second "Enable Transmit from Page fnn"
command. The COM20020 stores the fact that
the second transmit command was issued, along
with the page number.
Register will again be updated with the results of
the second transmission and a second interrupt
resulting from the second transmission will occur.
The COM20020 guarantees a minimum of 200ns
(at EF=1) interrupt inactive time interval before the
following edge.
After the first transmission is completed, the
COM20020 updates the Status Register by setting
the TTA bit, which generates an interrupt. The
interrupt service routine should read the Status
Register. At this point, the TTA bit will be found to
be a logic "1" and the TMA (Transmit Message
Acknowledge) bit will tell the processor whether
the transmission was successful. After reading
the Status Register, the "Clear Transmit Interrupt"
command is issued, thus resetting the TTA bit and
clearing the interrupt. Note that only the
"Clear Transmit Interrupt" command will clear the
TTA bit and the interrupt. It is not necessary,
however, to clear the bit or the interrupt right away
because the status of the transmit operation is
double buffered in order to retain the results of the
first transmission for analysis by the processor.
This information will remain in the Status Register
until the "Clear Transmit Interrupt" command is
issued. Note that the interrupt will remain active
until the command is issued, and the second
interrupt will not occur until the first interrupt is
acknowledged. The COM20020 guarantees a
minimum of 200nS (at EF=1) interrupt inactive
time interval between interrupts. The TMA bit is
also double buffered to reflect whether the
appropriate transmission was a success. The
TMA bit should only be considered valid after the
corresponding TTA bit has been set to a logic "1".
The TMA bit never causes an interrupt.
When the token is received again, the second
transmission will be automatically initiated after
the first is completed by using the stored "Enable
Transmit from Page fnn" command. The operation
is as if a new "Enable Transmit from Page fnn"
command has just been issued. After the first
Transmit status bits are cleared, the Status
The Transmitter Available (TA) bit of the Interrupt
Mask Register now masks only the TTA bit of the
Status Register, not the TA bit as in the non-
chaining mode. Since the TTA bit is only set upon
transmission of a packet (not by RESET), and
since the TTA bit may easily be reset by issuing a
"Clear Transmit Interrupt" command, there is no
need to use the TA bit of the Interrupt Mask
Register to mask interrupts generated by the TTA
bit of the Status Register.
In Command Chaining mode, the "Disable
Transmitter" command will cancel the oldest
transmission. This permits canceling a packet
destined for a node not ready to receive. If both
packets should be canceled, two "Disable
Transmitter" commands should be issued.
Receive Command Chaining
Like the Transmit Command Chaining operation,
the processor can issue two consecutive "Enable
Receive from Page fnn" commands.
After the first packet is received into the first
specified page, the TRI bit of the Status Register
will be set to logic "1", causing an interrupt.
Again, the interrupt need not be serviced
immediately. Typically, the interrupt service
routine will read the Status Register. At this point,
the RI bit will be found to be a logic "1". After
reading the Status Register, the "Clear Receive
Interrupt" command should be issued, thus
resetting the TRI bit and clearing the interrupt.
Note that only the "Clear Receive Interrupt"
command will clear the TRI bit and the interrupt. It
is not necessary, however, to clear the bit or the
interrupt right away because the status of the
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