COM20020_00 Datasheet, PDF (18/82 Pages) SMSC Corporation – Universal Local Area Network Controller with 2K x 8 On-Board RAM

The above sampling and delaying signals are
supplied to the Read Pulse Generation logic
which generates the clearing pulse for the
Diagnostic register and generates the starting
pulse of the RAM Arbitration. Typical delay time
between nRD and nRD1 is around 15nS and
between nRD1 and nRD2 is around 10nS.
RBUSTMG=1, Enabled.
In the MOTOROLA CPU mode (DIR, nDS
mode), the same modifications apply.
Longer pulse widths are needed due to these
delays on nRD signal. However, the CPU can
insert some wait cycles to extend the width
without any impact on performance.
The RBUSTMG bit was added to Disable/Enable
the High Speed CPU Read function. It is defined
as: RBUSTMG=0, Disabled (Default);
RBUSTMG BIT
BUS TIMING MODE
0
Normal Speed CPU Read and Write
1
High Speed CPU Read and Normal Speed CPU Write
TRANSMISSION MEDIA INTERFACE
The bottom halves of Figures 2 and 3 illustrate the
COM20020 interface to the transmission media
used to connect the node to the network. Table 1
lists different types of cable which are suitable for
ARCNET applications.¹ The user may interface to
the cable of choice in one of three ways:
signals are sent to the Hybrid, which creates a
200nS dipulse signal on the media.
Traditional Hybrid Interface
The Traditional Hybrid Interface is that which is
used with previous ARCNET devices. The Hybrid
Interface is recommended if the node is to be
placed in a network with other Hybrid-Interfaced
nodes. The Traditional Hybrid Interface is for use
with nodes operating at 2.5 Mbps only. The
transformer coupling of the Hybrid offers isolation
for the safety of the system and offers high
Common Mode Rejection. The Traditional Hybrid
Interface uses circuits like SMSC's HYC9068 or
HYC9088 to transfer the pulse-encoded data
between the cable and the COM20020. The
COM20020 transmits a logic "1" by generating two
100nS non-overlapping negative pulses,
nPULSE1 and nPULSE2. Lack of pulses
indicates a logic "0". The nPULSE1 and nPULSE2
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