LAN83C185_08 Datasheet, PDF (53/60 Pages) SMSC Corporation – High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
6.4 Reset Timing
nRST
Configuration
signals
Output drive
T6.1
T6.2 T6.3
T6.4
PARAMETER
DESCRIPTION
T6.1
T6.2
T6.3
Reset Pulse Width
Configuration input setup to
nRST rising
Configuration input hold after
nRST rising
T6.4
Output Drive after nRST rising
MIN
100
200
400
20
TYP MAX UNITS
us
ns
NOTES
ns
800 ns
20 clock cycles for
25 MHz clock
SMSC LAN83C185
53
DATASHEET
Revision 0.8 (06-12-08)