LAN83C185_08 Datasheet, PDF (17/60 Pages) SMSC Corporation – High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is
bypassed the 5^th transmit data bit is equivalent to TX_ER.
Note that encoding can be bypassed only when the MAC interface is configured to operate in MII
mode.
Table 4.1 4B/5B Code Table
CODE
GROUP
SYM
RECEIVER
INTERPRETATION
TRANSMITTER
INTERPRETATION
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
11111
11000
10001
01101
00111
00100
00110
11001
00000
00001
0
0
0000
DATA
0
0000
DATA
1
1
0001
1
0001
2
2
0010
2
0010
3
3
0011
3
0011
4
4
0100
4
0100
5
5
0101
5
0101
6
6
0110
6
0110
7
7
0111
7
0111
8
8
1000
8
1000
9
9
1001
9
1001
A
A
1010
A
1010
B
B
1011
B
1011
C
C
1100
C
1100
D
D
1101
D
1101
E
E
1110
E
1110
F
F
1111
F
1111
I
IDLE
Sent after /T/R until TX_EN
J
First nibble of SSD, translated to “0101” Sent for rising TX_EN
following IDLE, else RX_ER
K
Second nibble of SSD, translated to
Sent for rising TX_EN
“0101” following J, else RX_ER
T
First nibble of ESD, causes de-assertion Sent for falling TX_EN
of CRS if followed by /R/, else assertion
of RX_ER
R
Second nibble of ESD, causes
Sent for falling TX_EN
deassertion of CRS if following /T/, else
assertion of RX_ER
H
Transmit Error Symbol
Sent for rising TX_ER
V
INVALID, RX_ER if during RX_DV
INVALID
V
INVALID, RX_ER if during RX_DV
INVALID
V
INVALID, RX_ER if during RX_DV
INVALID
V
INVALID, RX_ER if during RX_DV
INVALID
SMSC LAN83C185
17
DATASHEET
Revision 0.8 (06-12-08)