LAN83C185_08 Datasheet, PDF (38/60 Pages) SMSC Corporation – High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 5.42 Register 17 - Mode Control/Status (continued)
ADDRESS
NAME
DESCRIPTION
MODE DEFAULT
17.8
17.7:5
17.4
17.3
17.2
17.1
17.0
FASTEST
Auto-Negotiation Test Mode
0 = normal operation
1 = activates test mode
RW
0
Reserved
Write as 0, ignore on read.
Reserved
Reserved
Must be left at 0
RW
0
PHYADBP
1 = PHY disregards PHY address in SMI access
write.
RW
0
Force
0 = normal operation;
Good Link Status 1 = force 100TX- link active;
RW
0
Note: This bit should be set only during lab testing
ENERGYON
ENERGYON – indicates whether energy is detected RO
1
on the line (see Section 5.4.5.2, "Energy Detect
Power-Down," on page 43); it goes to “0” if no valid
energy is detected within 256ms. Reset to “1” by
hardware reset, unaffected by SW reset.
Reserved
Write as “0”. Ignore on read.
RW
0
ADDRESS
NAME
18.15:14 MIIMODE
18.13
CLKSELFREQ
18.12
18.11
18.10
18.9
18.8
18.7:5
DSPBP
SQBP
Reserved
PLLBP
ADCBP
MODE
Table 5.43 Register 18 - Special Modes
DESCRIPTION
MODE DEFAULT
MII Mode: set the mode of the MII:
0 – MII interface.
1 – Reserved
RW,
NASR
Clock In Selected Frequency. Set the requested input
clock frequency. This bit drives signal that goes to
external logic of the Phy and select the desired
frequency of the input clock:
0 – the clock frequency is 25MHz
1 – Reserved
RO,
NASR
DSP Bypass mode. Used only in special lab tests.
RW,
0
NASR
SQUELCH Bypass mode.
RW,
0
NASR
RW,
NASR
PLL Bypass mode.
RW,
NASR
ADC Bypass mode.
RW,
NASR
PHY Mode of operation. Refer to Section 5.4.9.2,
"Mode Bus – MODE[2:0]," on page 46 for more
details.
RW,
NASR
Revision 0.8 (06-12-08)
38
DATASHEET
SMSC LAN83C185