LAN8710 Datasheet, PDF (47/79 Pages) SMSC Corporation – MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology in a Small Footprint

MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR^® Technology in a Small Footprint
Datasheet
5.2
Interrupt Management
The Management interface supports an interrupt capability that is not a part of the IEEE 802.3
specification. It generates an active low asynchronous interrupt signal on the nINT output whenever
certain events are detected as setup by the Interrupt Mask Register 30.
The Interrupt system on the SMSC The LAN8710 has two modes, a Primary Interrupt mode and an
Alternative Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask
bit is set, the difference is how they de-assert the output interrupt signal nINT.
The Primary interrupt mode is the default interrupt mode after a power-up or hard reset, the Alternative
interrupt mode would need to be setup again after a power-up or hard reset.
5.2.1 Primary Interrupt System
The Primary Interrupt system is the default interrupt mode, (Bit 17.6 = ‘0’). The Primary Interrupt
System is always selected after power-up or hard reset.
To set an interrupt, set the corresponding mask bit in the interrupt Mask register 30 (see Table 5.37).
Then when the event to assert nINT is true, the nINT output will be asserted.
When the corresponding Event to De-Assert nINT is true, then the nINT will be de-asserted.
Table 5.37 Interrupt Management Table
MASK
INTERRUPT SOURCE
FLAG
30.7
29.7 ENERGYON
30.6
29.6 Auto-Negotiation
complete
30.5
29.5 Remote Fault
Detected
INTERRUPT SOURCE
17.1 ENERGYON
1.5 Auto-Negotiate
Complete
1.4 Remote Fault
EVENT TO
ASSERT nINT
Rising 17.1
(Note 5.1)
Rising 1.5
Rising 1.4
30.4
29.4 Link Down
1.2 Link Status
Falling 1.2
30.3
29.3 Auto-Negotiation
5.14 Acknowledge
LP Acknowledge
Rising 5.14
30.2
29.2 Parallel Detection 6.4
Parallel
Rising 6.4
Fault
Detection Fault
30.1
29.1 Auto-Negotiation
6.1
Page Received Rising 6.1
Page Received
EVENT TO
DE-ASSERT nINT
Falling 17.1 or
Reading register 29
Falling 1.5 or
Reading register 29
Falling 1.4, or
Reading register 1 or
Reading register 29
Reading register 1 or
Reading register 29
Falling 5.14 or
Read register 29
Falling 6.4 or
Reading register 6, or
Reading register 29
or
Re-Auto Negotiate or
Link down
Falling of 6.1 or
Reading register 6, or
Reading register 29
Re-Auto Negotiate, or
Link Down.
Note 5.1
If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high,
nINT will assert for 256 ms, approximately one second after ENERGYON goes low when
the Cable is unplugged. To prevent an unexpected assertion of nINT, the ENERGYON
interrupt mask should always be cleared as part of the ENERGYON interrupt service
routine.
SMSC LAN8710/LAN8710i
47
DATASHEET
Revision 1.0 (04-15-09)