LAN91C100FD_08 Datasheet, PDF (34/77 Pages) SMSC Corporation – FEAST Fast Ethernet Controller with Full Duplex Capability

FEAST Fast Ethernet Controller with Full Duplex Capability
Note:
READ - Determines the type of access to follow. If the READ bit is high the operation intended is a read. If
the READ bit is low the operation is a write. Loading a new pointer value, with the READ bit high,
generates a pre-fetch into the Data Register for read purposes.
Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than the
last pre-fetched). This allows any interrupt routine that uses the pointer, to save it and restore it without
affecting the process being interrupted. The Pointer Register should not be loaded until the Data Register FIFO is
empty. The NOT EMPTY bit of this register can be read to determine if the FIFO is empty. On reads, if IOCHRDY is
not connected to the host, the Data Register should not be read before 370ns after the pointer was loaded to allow the
Data Register FIFO to fill.
If the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last.
Reserved – Must be 0.
NOT EMPTY - When set indicates that the Write Data FIFO is not empty yet. The CPU can verify that the
FIFO is empty before loading a new pointer value. This is a read only bit.
If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value.
BANK 2
OFFSET
8 THROUGH BH
X
X
X
X
NAME
DATA REGISTER
DATA HIGH
X
X
X
DATA LOW
X
X
X
TYPE
READ/WRITE
X
X
SYMBOL
DATA
X
X
X
X
DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer
register.
This register is mapped into two uni-directional FIFOs that allow moving words to and from the
LAN91C100FD regardless of whether the pointer address is even, odd or dword aligned. Data goes
through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses
are used, the appropriate (next) byte can be accessed through the Data Low or Data High registers. The
order to and from the FIFO is preserved. Byte, word and dword accesses can be mixed on the fly in any
order.
This register is mapped into two consecutive word locations to facilitate double word move operations
regardless of the actual bus width (16 or 32 bits). The DATA register is accessible at any address in the 8
through Ah range, while the number of bytes being transferred is determined by A1 and nBE0-nBE3. The
FIFOs are 12 bytes each.
BANK 2
OFFSET
C
NAME
INTERRUPT STATUS REGISTER
TYPE
READ ONLY
RX_DISC
INT
0
Reserved
0
EPH INT
0
RX_OVRN
INT
0
ALLOC
INT
0
TX EMPTY
INT
1
SYMBOL
IST
TX INT
0
RCV INT
0
Revision 1.0 (09-22-08)
Page 34
DATASHEET
SMSC LAN91C100FD Rev. D