LAN91C100FD_08 Datasheet, PDF (23/77 Pages) SMSC Corporation – FEAST Fast Ethernet Controller with Full Duplex Capability

FEAST Fast Ethernet Controller with Full Duplex Capability
BANK 0
OFFSET
0
NAME
TRANSMIT CONTROL
REGISTER
TYPE
READ/WRITE
SYMBOL
TCR
This register holds bits programmed by the CPU to control some of the protocol transmit options.
HIGH SWFDU
0
BYTE
P
0
0
LOW PAD_EN
0
BYTE
0
0
EPH
LOOP
0
0
0
STP
SQET
0
0
0
FDUPLX
0
0
MON_
CSN
0
FORCOL
0
0
LOOP
0
0
0
NOCRC
0
TXENA
0
SWFDUP - Enables Switched Full Duplex mode. In this mode, transmit state machine is inhibited from
recognizing carrier sense, so deferrals will not occur. Also inhibits collision count, therefore, the collision
related status bits in the EPHSR are not valid (CTR_ROL, LATCOL, SQET, 16COL, MUL COL, and
SNGL COL). Uses COL100 as flow control, limiting backoff and jam to 1 clock each before inter-frame
gap, then retry will occur after IFG. If COL100 is active during preamble, full preamble will be output
before jam. When SWFDUP is high, the values of FDUPLX and MON_CSN have no effect. This bit should
be low for non-MII operation.
EPH_LOOP - Internal loopback at the EPH block. Serial data is internally looped back when set. Defaults
low. When EPH_LOOP is high the following transmit outputs are forced inactive: TXD0-TXD3 = 0h,
TXEN100 = TXEN = 0, TXD = 1. The following and external inputs are blocked: CRS=CRS100=0,
COL=COL100=0, RX_DV= RX_ER=0.
STP_SQET - Stop transmission on SQET error. If set, stops and disables transmitter on SQE test error.
Does not stop on SQET error and transmits next frame if clear. Defaults low.
FDUPLX - When set, the LAN91C100FD will cause frames to be received if they pass the address filter
regardless of the source of the frame. When clear, the node will not receive a frame sourced by itself.
This bit does not control the duplex mode operation, the duplex mode operation is controlled by the
SWFDUP bit.
MON_CSN - When set the LAN91C100FD monitors carrier while transmitting. It must see its own carrier
by the end of the preamble. If it is not seen, or if carrier is lost during transmission, the transmitter aborts
the frame without CRC and turns itself off and sets the LOST CARR bit in the EPHSR. When this bit is
clear the transmitter ignores its own carrier. Defaults low. Should be 0 for MII operation.
NOCRC - Does not append CRC to transmitted frames when set. Allows software to insert the desired
CRC. Defaults to zero, namely CRC inserted.
PAD_EN - When set, the LAN91C100FD will pad transmit frames shorter than 64 bytes with 00. The CPU
should write the actual byte count (1 – 1514/1518) into the BYTE COUNT area in the transmit buffer RAM.
If the CPU provides the 4 byte CRC, the maximum byte count will be 1518. If the CPU elects to have the
LAN91C100FD provide the CRC, the maximum byte count will be 1514. The CPU should then write the
actual packet data in the DATA AREA of the transmit buffer RAM. The LAN91C100FD will then determine
if padding is necessary, (BYTE COUNT AREA less then 64). If padding is required, the LAN91C100FD will
append data bytes of 00 to meet the minimum requirement of 64 bytes. When this bit is cleared, the
LAN91C100FD does not pad frames.
FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set and
cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the FORCOL
bit is set, the LAN91C100FD will transmit a preamble pattern the next time a carrier is seen on the line. If a
packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal operation.
NOTE: The LATCOL bit in the EPHSR, setting up as a result of FORCOL, will reset TXENA to 0. In order
to force another collision, TXENA must be set to 1 again.
SMSC LAN91C100FD Rev. D
Page 23
DATASHEET
Revision 1.0 (09-22-08)