COM20020-5 Datasheet, PDF (30/58 Pages) SMSC Corporation – Universal Local Area Network Controller with 2K x 8 On-Board RAM

INTERNAL RAM
The integration of the 2K x 8 RAM in the
COM20020-5 represents significant real estate
savings. The most obvious benefit is the 24-pin
package in which the device is now placed (a
direct result of the integration of RAM). In
addition, the PC board is now free of the
cumbersome external RAM, external latch, and
multiplexed address/data bus and control
functions which were necessary to interface to
the RAM.
The integration of RAM represents significant
cost savings because it isolates the system
designer from the changing costs of external
RAM and it minimizes reliability problems,
assembly time and costs, and layout complexity.
Sequential Access Memory
The internal RAM is accessed via a pointer-
based scheme. Rather than interfering with
system memory, the internal RAM is indirectly
accessed through the Address High and Low
Pointer Registers. The data is channeled to and
from the microcontroller via the 8-bit data
register. For example: a packet in the internal
RAM buffer is read by the microcontroller by
writing the corresponding address into the
Address Pointer High and Low Registers (offsets
02H and 03H). Note that the High Register
should be written first, followed by the Low
Register, because writing to the Low Register
loads the address. At this point the device
accesses that location and places the
corresponding data into the data register. The
microcontroller then reads the data register
(offset 04H) to obtain the data at the specified
location. If the Auto Increment bit is set to logic
"1", the device will automatically increment the
address and place the next byte of data into
the data register, again to be read by the
microcontroller. This process is continued until
the
entire packet is read out of
RAM. Refer to Figure 6 for an illustration of the
Sequential Access operation.
When switching between reads and writes, the
pointer must first be written with the starting
address. At least one cycle time should
separate the pointer being loaded and the first
read (see timing parameters).
Access Speed
The COM20020-5 is able to accommodate very
fast access cycles to its registers and buffers.
Arbitration to the buffer does not slow down the
cycle because the pointer based access method
allows data to be prefetched from memory and
stored in a temporary register. Likewise,
data to be written is stored in the temporary
register and then written to memory.
For systems which do not require quick access
time, the arbitration clock may be slowed down
by setting bit 0 of the Setup Register equal to
logic "1". Since the Slow Arbitration feature
divides the input clock by two, the duty cycle of
the input clock may be relaxed.
SOFTWARE INTERFACE
The microcontroller interfaces to the
COM20020-5 via software by accessing the
various registers. These actions are described
in the Internal Registers section. The software
flow for accessing the data buffer is based on
the Sequential Access scheme. The basic
sequence is as follows:
• Disable Interrupts
• Write to Pointer Register High (specifying
Auto-Increment mode.)
• Write to Pointer Register Low (this loads
the address.)
• Enable Interrupts
• Read or write the Data Register (repeat as
many times as necessary to empty or fill
the buffer).
30