COM20020-5 Datasheet, PDF (18/58 Pages) SMSC Corporation – Universal Local Area Network Controller with 2K x 8 On-Board RAM

FUNCTIONAL DESCRIPTION
MICROSEQUENCER
Interrupt Mask Register (IMR)
The COM20020-5 contains an internal
microsequencer which performs all of the The COM20020-5 is capable of generating an
control operations necessary to carry out the interrupt signal when certain status bits become
ARCNET protocol. It consists of a clock true. A write to the IMR specifies which status
generator, a 544 x 8 ROM, a program counter, bits will be enabled to generate an interrupt. The
two instruction registers, an instruction decoder, bit positions in the IMR are in the same position
a no-op generator, jump logic, and as their corresponding status bits in the Status
reconfiguration logic.
Register and Diagnostic Status Register. A logic
"1" in a particular position enables the
The COM20020-5 derives a 10MHz and a 5MHz corresponding interrupt. The Status bits
clock from the external crystal. These clocks capable of generating an interrupt include the
provide the rate at which the instructions are Receiver Inhibited bit, New Next ID bit,
executed within the COM20020-5. The 10MHz Excessive NAK bit, Reconfiguration Timer bit,
clock is the rate at which the program counter and Transmitter Available bit. No other Status
operates, while the 5MHz clock is the rate at or Diagnostic Status bits can generate an
which the instructions are executed. The interrupt.
microprogram is stored in the ROM and the
instructions are fetched and then placed into the The five maskable status bits are ANDed with
instruction registers. One register holds the their respective mask bits, and the results are
opcode, while the other holds the immediate ORed to produce the interrupt signal. An RI
data. Once the instruction is fetched, it is or TA interrupt is masked when the
decoded by the internal instruction decoder, at corresponding mask bit is reset to logic "0", but
which point the COM20020-5 proceeds to will reappear when the corresponding mask bit
execute the instruction. When a no-op is set to logic "1" again, unless the interrupt
instruction is encountered, the microsequencer status condition has been cleared by this time.
enters a timed loop and the program counter is A RECON interrupt is cleared when the "Clear
temporarily stopped until the loop is complete.
Flags" command is issued. An EXCNAK
When a jump instruction is encountered, the interrupt is cleared when the "POR Clear Flags"
program counter is loaded with the jump command is issued. A New Next ID interrupt is
address from the ROM. The COM20020-5 cleared by reading the New Next ID Register.
contains an internal reconfiguration timer which The Interrupt Mask Register defaults to the
interrupts the microsequencer if it has timed out. value 0000 0000 upon either hardware or
At this point the program counter is cleared and software reset.
the MYRECON bit of the Diagnostic Status
Register is set.
Data Register
INTERNAL REGISTERS
The COM20020-5 contains eight internal
registers. Tables 1 and 2 illustrate the
COM20020-5 register map. Reserved locations
should not be accessed. All undefined bits
are read as undefined and must be written as
logic "0".
This read/write 8-bit register is used as the
channel through which the data to and from the
RAM passes. The data is placed in or retrieved
from the address location presently specified by
the address pointer. The contents of the Data
Register are undefined upon hardware reset. In
case of READ operation, the Data Register is
loaded with the contents of COM20020-5
18