LPC47M172_07 Datasheet, PDF (162/226 Pages) SMSC Corporation – Advanced I/O Controller with Motherboard GLUE Logic

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
REGISTER
OFFSET
(HEX)
25
26
27
28
29
2A
2B
2C
2D-34
35
36
37-3F
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R
PCI RESET
-
-
-
-
-
-
-
-
-
-
-
-
VCC POR VTR POR
-
0x01
-
0x01
-
0x01
-
0x04
-
0x04
-
0x04
-
0x04
-
0x05
-
-
-
0x00
-
0x00
-
-
SOFT
RESET
-
-
-
-
-
-
-
-
-
-
-
-
REGISTER
GP15
GP16
GP17
GP20
GP21
GP22
GP23
GP24
Reserved – reads return 0
GP1
GP2
Reserved – reads return 0
NAME
PME_STS
Default = 0x00
on VTR POR
N/A
PME_EN
Default = 0x00
on VTR POR
N/A
Table 10.2 - Runtime Register Block Runtime Registers Description
REG OFFSET
(Type)
0x00
(R/W)
0x01 – 0x03
(R)
0x04
(R/W)
0x05 – 0x07
(R)
DESCRIPTION
Bit[0] PME_Status
= 0 (default)
= 1 Set when LPC47M172 would normally assert the nIO_PME signal,
independent of the state of the PME_En bit.
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET.
Writing a “1” to PME_Status will clear it and cause the LPC47M172 to stop
asserting nIO_PME, in enabled. Writing a “0” to PME_Status has no effect.
Bits[7:0] Reserved – reads return 0
Bit[0] PME_En
= 0 nIO_PME signal assertion is disabled (default)
= 1 Enables LPC47M172 to assert nIO_PME signal
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or HARD RESET
Bits[7:0] Reserved – reads return 0
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Page 162
DATASHEET
SMSC LPC47M172