LPC47M172_07 Datasheet, PDF (117/226 Pages) SMSC Corporation – Advanced I/O Controller with Motherboard GLUE Logic

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.25.14 Interrupts
The LPC47M172 provides the two 8042 interrupts: IBF and the Timer/Counter Overflow.
7.25.15 Memory Configurations
The LPC47M172 provides 2K of on-chip ROM and 256 bytes of on-chip RAM.
7.25.16 Register Definitions
Host I/F Data Register
The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load
the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this
register will read the data from the Keyboard Data or Command Write Buffer and clear the IBF flag. Refer
to the KIRQ and Status register descriptions for more information.
Host I/F Status Register
The Status register is 8 bits wide.
Table 7.12 shows the contents of the Status register.
D7
D6
UD
UD
Status Register
Table 7.12 - Status Register
D5
D4
D3
D2
UD
UD
C/D
UD
D1
D0
IBF
OBF
This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47M172
CPU.
UD Writable by LPC47M172 CPU. These bits are user-definable.
C/D (Command Data)-This bit specifies whether the input data register contains data or a command (0
= data, 1 = command). During a host data/command write operation, this bit is set to “1” if SA2 = 1
or reset to “0” if SA2 = 0.
IBF (Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data
register. Setting this flag activates the LPC47M172 CPU’s nIBF (MIRQ) interrupt if enabled. When
the LPC47M172 CPU reads the input data register (DBB), this bit is automatically reset and the
interrupt is cleared. There is no output pin associated with this internal signal.
OBF (Output Buffer Full) - This flag is set to whenever the LPC47M172 CPU write to the output data
register (DBB). When the host system reads the output data register, this bit is automatically reset.
SMSC LPC47M172
Page 117
DATASHEET
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)