LPC47M172_07 Datasheet, PDF (111/226 Pages) SMSC Corporation – Advanced I/O Controller with Motherboard GLUE Logic

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge
hierarchy in a synchronous bridge design.
B) Stop Frame Timing with Host using 17 SER_IRQ sampling period
IRQ14
FRAME
SRT
IRQ15
FRAME
SRT
IOCHCK#
FRAME
SRT
STOP FRAME
I^{2 H}
RT
NEXT CYCLE
PCI_CLK
SER_IRQ
STOP¹
START ³
Driver ^None
IRQ15
None
Host Controller
Note: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-around clock
of the Stop Frame.
Note 2: There may be none, one or more Idle states during the Stop Frame.
Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
7.23.2 SER_IRQ Cycle Control
There are two modes of operation for the SER_IRQ Start Frame:
1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock,
while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated
without at any time driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The
SER_IRQ is Idle between Stop and Start Frames. The SER_IRQ is Active between Start and Stop
Frames. This mode of operation allows the SER_IRQ to be Idle when there are no IRQ/Data transitions
which should be most of the time.
Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the
next clock and will continue driving the SER_IRQ low for a programmable period of three to seven clocks.
This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the
SER_IRQ back high for one clock, then tri-state.
If LPC47M172 detects any transition on an IRQ/Data line for which it is responsible, it initiates a Start
Frame in order to update the Host Controller unless the SER_IRQ is already in an SER_IRQ Cycle and the
IRQ/Data transition can be delivered in that SER_IRQ Cycle
2) Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line
information. All other SER_IRQ agents become passive and may not initiate a Start Frame. SER_IRQ will
be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be used to
stop or idle the SER_IRQ or the Host Controller can operate SER_IRQ in a continuous mode by initiating a
Start Frame at the end of every Stop Frame.
An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ bus is
defaulted to Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves
must continuously sample the Stop Frames pulse width to determine the next SER_IRQ Cycle’s mode.
SMSC LPC47M172
Page 111
DATASHEET
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)