LPC47B34X Datasheet, PDF (115/250 Pages) SMSC Corporation – 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications

For ACPI compliance the FDD pins that are multiplexed onto the Parallel Port function independently
of the state of the Parallel Port controller. For example, if the FDC is enabled onto the Parallel Port
the multiplexed FDD interface functions normally regardless of the Parallel Port Power control,
CR22.3. Table 39 illustrates this functionality.
TABLE 39 - MODIFIED PARALLEL PORT FDD CONTROL
PARALLEL PORT
PARALLEL PORT FDC
PARALLEL PORT
PARALLEL
POWER
CONTROL
FDC STATE
PORT STATE
CR22.3
LD3:CRF1.1
LD3:CRF1.0
1
0
0
OFF
ON
0
0
0
OFF
OFF
X
1
X
ON
OFF
X
1
(NOTE¹)
NOTE¹: The Parallel Port Control register reads as “Cable Not Connected” when the Parallel Port
FDC is enabled; i.e., STROBE = AUTOFD = SLC = 0 and nINIT = 1.
Table 40 - FDC Parallel Port Pins
CONNECTOR
QFP
PIN
PIN #
CHIP PIN # SPP MODE DIRECTION FDC MODE
1
98
nSTROBE
I/O
(nDS0)
2
83
PD0
I/O
nINDEX
3
84
PD1
I/O
nTRK0
4
85
PD2
I/O
nWP
5
86
PD3
I/O
nRDATA
6
88
PD4
I/O
nDSKCHG
7
89
PD5
I/O
-
8
90
PD6
I/O
(nMTR0)
9
91
PD7
I/O
-
10
95
nACK
I
nDS1
11
94
BUSY
I
nMTR1
12
93
PE
I
nWDATA
13
92
SLCT
I
nWGATE
14
97
nALF
I/O
DRVDEN0
15
96
nERROR
I
nHDSEL
16
81
nINIT
I/O
nDIR
17
82
nSLCTIN
I/O
nSTEP
Note 1: These pins are outputs in mode PPFD2, inputs in mode PPFD1.
PIN
DIRECTION
I/(O) Note1
I
I
I
I
I
-
I/(O) Note1
-
O
O
O
O
O
O
O
O
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