LPC47B34X Datasheet, PDF (104/250 Pages) SMSC Corporation – 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications

NAME
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
Table 35 - ECP Register Definitions
ADDRESS (Note 1)
ECP MODES
+000h R/W
000-001
+000h R/W
011
+001h R/W
All
+002h R/W
All
+400h R/W
010
+400h R/W
011
+400h R/W
110
+400h R
111
+401h R/W
111
+402h R/W
All
FUNCTION
Data Register
ECP FIFO (Address)
Status Register
Control Register
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
Note 1: These addresses are added to the parallel port base address as selected by configuration
register or jumpers.
Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.
MODE
000
001
010
011
100
101
110
111
Table 36 - Mode Descriptions
DESCRIPTION*
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the configuration registers)
Reserved
Test mode
Configuration mode
*Refer to ECR Register Description
Data And ecpAFifo Port
ADDRESS OFFSET = 00H
Modes 000 and 001 (Data Port)
The Data Port is located at an offset of '00H' from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data
bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.
During a READ operation, PD0 - PD7 ports are read and output to the host CPU.
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