U637256 Datasheet, PDF (8/14 Pages) List of Unclassifed Manufacturers – CapStore 32K x 8 nvSRAM

U637256
PowerStore and automatic Power Up RECALL
V_CC
5.0 V
V_SWITCH
PowerStore
Power Up
RECALL
W
DQi
(24)
t_RESTORE
t
(25)
t_PDSTORE
(24)
t_RESTORE
t_DELAY
POWER UP BROWN OUT
BROWN OUT
RECALL
NO STORE
PowerStore
(NO SRAM WRITES)
No.
Software Controlled STORE/RECALL
Cycle^{k, o}
Symbol
Alt.
IEC
Min.
Max.
Unit
27 STORE/RECALL Initiation Time
t_AVAV
t_cR
70
28 Chip Enable to Output Inactive^p
t_ELQZ
t_dis(E)SR
29 STORE Cycle Time^q
t_ELQXS
t_d(E)S
30 RECALL Cycle Time^r
t_ELQXR
t_d(E)R
31 Address Setup to Chip Enable^s
t_AVELN
t_su(A)SR
0
32 Chip Enable Pulse Width^{s, t}
t_ELEHN
t_w(E)SR
60
33 Chip Disable to Address Change^s
t_EHAXN
t_h(A)SR
0
ns
600
ns
10
ms
20
μs
ns
ns
ns
o: The software sequence is clocked with E controlled READs.
p: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
q: Note that STORE cycles (but not RECALL) are inhibited by V_CC < V_SWITCH (STORE inhibit).
r: An automatic RECALL also takes place at power up, starting when V_CC exceeds V_SWITCH and takes t_RESTORE. V_CC must not drop below
V_SWITCH once it has been exceeded for the RECALL to function properly.
s: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
t: If the Chip Enable Pulse Width is less than t_a(E) (see Read Cycle) but greater than or equal t_w(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
STK Control #ML0054
8
Rev 1.1
August 15, 2006