U637256 Datasheet, PDF (11/14 Pages) List of Unclassifed Manufacturers – CapStore 32K x 8 nvSRAM

U637256
Device Operation
The U637256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory ope-
rates in SRAM mode as a standard static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below V_SWITCH. RECALL operations are automatically
initiated upon power up and may also occur when the
V_CC rises above V_SWITCH, after a low power condition.
RECALL cycles may also be initiated by a software
sequence.
In order to prevent unneeded STORE operations, auto-
matic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether or
not a WRITE operation has taken place.
SRAM READ and WRITE operations that are in pro-
gress after an automatic STORE cycle on power down
is requested are given time to complete before the
STORE operation is initiated.
During t_DELAY multiple SRAM READ operations may
take place. If a WRITE is in progress it will be allowed a
time, t_DELAY, to complete. Any SRAM WRITE cycles
requested after the V_CC pin drops below V_SWITCH will be
inhibited.
Automatic RECALL
SRAM READ
The U637256 performs a READ cycle whenever E and
G are LOW and W is HIGH. The address specified on
pins A0 - A14 determines which of the 32768 data
bytes will be accessed. When the READ is initiated by
an address transition, the outputs will be valid after a
delay of t_cR. If the READ is initiated by E or G, the out-
puts will be valid at t_a(E) or at t_a(G), whichever is later.
The data outputs will repeatedly respond to address
changes within the t_cR access time without the need for
transition on any control input pins, and will remain
valid until another address change or until E or G is
brought HIGH or W is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid t_su(D) before the end of a W controlled WRITE or
t_su(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers t_{dis (W)} after W goes LOW.
Automatic STORE
During normal operation, the U637256 will draw current
from V_CC to charge up an integrated capacitor. This
stored charge will be used by the chip to perform a sin-
gle STORE operation. If the voltage on the V_CC pin
drops below V_SWITCH, the part will automatically discon-
nect the internal components from the external power
supply with a typical delay of 150 ns and initiate a
STORE operation with t_PDSTORE max. 10 ms.
During power up, an automatic RECALL takes place. At
a low power condition (power supply voltage < V_SWITCH)
an internal RECALL request may be latched. As soon
as power supply voltage exceeds the sense voltage of
V_SWITCH, a requested RECALL cycle will automatically
be initiated and will take t_RESTORE to complete.
If the U637256 is in a WRITE state at the end of power
up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and power supply voltage.
Software Nonvolatile STORE
The U637256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U637256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all the nonvolatile elements.
Once a STORE cycle is initiated, further inputs and out-
puts are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
1. Read addresses 0E38 (hex) Valid READ
2. Read addresses 31C7 (hex) Valid READ
3. Read addresses 03E0 (hex) Valid READ
4. Read addresses 3C1F (hex) Valid READ
5. Read addresses 303F (hex) Valid READ
6. Read addresses 0FC0 (hex) Initiate STORE
Cycle
August 15, 2006
STK Control #ML0054
11
Rev 1.1