U637256 Datasheet, PDF (5/14 Pages) List of Unclassifed Manufacturers – CapStore 32K x 8 nvSRAM

Read Cycle 1: Ai-controlled (during Read cycle: E = G = V_IL, W = V_IH)^f
Ai
DQi
Output
t_{cR (1)}
Address Valid
t_{a(A) (2)}
Previous Data Valid
t_{v(A) (9)}
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = V_IH)^g
Ai
E
G
DQi
Output
I_CC
t_{cR (1)}
Address Valid
t_{a(A) (2)}
t_a(E) (3)
t_{en(E) (7)}
t_a(G) (4)
High Impedance
ACTIVE
STANDBY
t_{en(G) (8)}
t_PU (10)
t_dis(E) (5)
t_PD (11)
t_{dis(G) (6)}
Output Data Valid
U637256
No.
Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Z^{h, i}
23 W HIGH to Output in Low-Z
Symbol
Alt. #1 Alt. #2 IEC
t_AVAV
t_WLWH
t_AVWL
t_AVWH
t_ELWH
t_DVWH
t_WHDX
t_WHAX
t_WLQZ
t_WHQX
t_AVAV
t_cW
t_w(W)
t_WLEH t_su(W)
t_AVEL
t_su(A)
t_AVEH t_su(A-WH)
t_su(E)
t_ELEH
t_w(E)
t_DVEH
t_su(D)
t_EHDX
t_h(D)
t_EHAX
t_h(A)
t_dis(W)
t_en(W)
Min.
70
55
55
0
55
55
55
30
0
0
5
August 15, 2006
STK Control #ML0054
5
Rev 1.1
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
ns
ns