U637256 Datasheet, PDF (7/14 Pages) List of Unclassifed Manufacturers – CapStore 32K x 8 nvSRAM

U637256
Nonvolatile Memory Operations
Mode Selection
E
W
A13 - A0
(hex)
Mode
H
X
X
Not Selected
L
H
X
Read SRAM
L
L
X
Write SRAM
L
H
0E38
Read SRAM
31C7
Read SRAM
03E0
Read SRAM
3C1F
Read SRAM
303F
Read SRAM
0FC0 Nonvolatile STORE
L
H
0E38
Read SRAM
31C7
Read SRAM
03E0
Read SRAM
3C1F
Read SRAM
303F
Read SRAM
0C63 Nonvolatile RECALL
I/O
Output High Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Power
Standby
Active
Active
Active
Active
Note
s
m
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k, l
k: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l: While there are 15 addresses on the U637256, only the lower 14 are used to control software modes.
Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G ≤ V_IL.
No.
PowerStore
Power Up RECALL
24 Power Up RECALL Durationⁿ
25 STORE Cycle Duration^{f, e}
26
Time allowed to Complete SRAM
Cycle^f
Low Voltage Trigger Level
Symbol
Alt.
IEC
t_RESTORE
t_PDSTORE
t_DELAY
V_SWITCH
n: t_RESTORE starts from the time V_CC rises above V_SWITCH.
Conditions
Min. Max. Unit
650 μs
10 ms
1
μs
4.0 4.5 V
August 15, 2006
STK Control #ML0054
7
Rev 1.1