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U634H256 Datasheet, PDF (8/15 Pages) Zentrum Mikroelektronik Dresden AG – POWERSTORE 32K X 8 NVSRAM
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U634H256
PowerStore and Automatic Power Up RECALL
VCAP
5.0 V
VSWITCH
t
PowerStore
Power Up
RECALL
W
DQi
(24)
tRESTORE
tPDSTOREp
(24)
tRESTORE
tDELAYp
Hardware Controlled STORE
POWER UP BROWN OUT
BROWN OUT
RECALL NO STORE
PowerStore
(NO SRAM WRITES)
HSB
DQi
Output
tw(H)Sq (28)
tdis(H)S (26)
Previous Data Valid
td(H)S (25)
ten(H)S (27)
High Impedance
Data Valid
No.
Software
Cycle
Controlled
STORE/RECALL
Symbol
Alt.
IEC
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
29 STORE/RECALL Initiation Time
30 Chip Enable to Output Inactives
31 STORE Cycle Time
32 RECALL Cycle Timer
33 Address Setup to Chip Enablet
34 Chip Enable Pulse Widths, t
35 Chip Disable to Address Changet
tAVAV
tELQZ
tELQXS
tELQXR
tAVELN
tELEHN
tEHAXN
tcR
25
35
45
ns
tdis(E)SR
600
600
600 ns
td(E)S
10
10
10 ms
td(E)R
20
20
20 μs
tsu(A)SR
0
0
0
ns
tw(E)SR 20
25
30
ns
th(A)SR
0
0
0
ns
p: tPDSTORE approximate td(E)S or td(H)S; tDELAY approximate tdis(H)S.
q: After tw(H)S HSB is hold down internal by STORE operation.
r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
s: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
t: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
STK Control #ML0048
8
Rev 1.1
August 15, 2006
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