U634H256 Datasheet, PDF (1/15 Pages) Zentrum Mikroelektronik Dresden AG – POWERSTORE 32K X 8 NVSRAM

Not Recommended For New Designs
U634H256
PowerStore 32K x 8 nvSRAM
Features
Description
‡ High-performance CMOS non- The U634H256 has two separate
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode
‡ 25, 35 and 45 ns Access Times and nonvolatile mode. In SRAM
‡ 10, 15 and 20 ns Output Enable mode, the memory operates as an
Access Times
‡ I_CC = 15 mA typ. at 200 ns Cycle
Time
‡ Automatic STORE to EEPROM
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
on Power Down using external mode SRAM functions are disab-
capacitor
‡ Hardware or Software initiated
led.
The U634H256 is a fast static RAM
STORE
(25, 35, 45 ns), with a nonvolatile
(STORE Cycle Time < 10 ms)
‡ Automatic STORE Timing
‡ 10⁶ STORE cycles to EEPROM
‡ 100 years data retention in
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
EEPROM
unlimited number of times, while
‡ Automatic RECALL on Power Up independent nonvolatile data resi-
‡ Software RECALL Initiation
des in EEPROM. Data transfers
(RECALL Cycle Time < 20 μs)
‡ Unlimited RECALL cycles from
from the SRAM to the EEPROM
(the STORE operation) take place
EEPROM
‡ Single 5 V ± 10 % Operation
‡ Operating temperature ranges:
automatically upon power down
using charge stored in an external
100 μF capacitor.
0 to 70 °C
Transfers from the EEPROM to the
-40 to 85 °C
SRAM (the RECALL operation)
-40 to125 °C(only 35 ns)
‡ QS 9000 Quality Standard
‡ ESD protection > 2000 V
take place automatically on power
up.
The U634H256 combines the high
(MIL STD 883C M3015.7-HBM) performance and ease of use of a
‡ RoHS compliance and Pb- free fast SRAM with nonvolatile data
Package: SOP32 (300 mil)
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence or via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
VCAP 1
32
A14 2
31
A12 3
30
A7 4
29
A6 5
28
A5 6
27
A4 7
26
A3 8
25
SOP ^{n.c. 9}
24
A2 10
23
A1 11
22
A0 12
21
DQ0 13
20
DQ1 14
19
DQ2 15
18
VSS 16
17
VCCX
HSB
W
A13
A8
A9
A11
G
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Description
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Controlled Store/Busy
Top View
August 15, 2006
STK Control #ML0048
1
Rev 1.1