U634H256 Datasheet, PDF (6/15 Pages) Zentrum Mikroelektronik Dresden AG – POWERSTORE 32K X 8 NVSRAM

U634H256
Write Cycle #1: W-controlled^j
Ai
E
W
DQi
Input
DQi
Output
t_{cW (12)}
Address Valid
t_su(E) (17)
t_{h(A) (21)}
t_su(A)
(15)
t_{su(A-WH) (16)}
t_w(W) (13)
t_{su(D) (19)}
t_{h(D) (20)}
Previous Data
t_dis(W) (22)
Input Data Valid
t_{en(W) (23)}
High Impedance
Write Cycle #2: E-controlled^j
Ai
E
W
DQi
Input
DQi
Output
t_su(A)
(15)
t_{cW (12)}
Address Valid
t_{w(E) (18)}
t_{h(A) (21)}
t_{su(W) (14)}
t_{su(D) (19)}
t_{h(D) (20)}
Input Data Valid
High Impedance
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E or W must be V_IH during address transition.
STK Control #ML0048
6
Rev 1.1
August 15, 2006