U630H16P Datasheet, PDF (6/17 Pages) Simtek Corporation – HardStore 2K x 8 nvSRAM

U630H16P
Write Cycle #1: W-controlled^j
Ai
E
W
DQi
Input
DQi
Output
t_{cW (12)}
Address Valid
t_{su(E) (17)}
t_{h(A) (21)}
t_su(A)
(15)
t_{su(A-WH) (16)}
t_{w(W) (13)}
t_{su(D) (19)}
t_{h(D) (20)}
t_dis(W)
(22)
Previous Data
Input Data Valid
High Impedance
t_{en(W) (23)}
Write Cycle #2: E-controlled^j
Ai
E
W
DQi
Input
DQi
Output
t_{su(A) (15)}
t_{cW (12)}
Address Valid
t_{w(E) (18)}
t_h(A) (21)
t_{su(W) (14)}
t_{en(E) (7)}
t_{dis(W) (22)}
t_{su(D) (19)}
t_{h(D) (20)}
Input Data Valid
High Impedance
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E or W and NE must be > V_IH during address transitions.
STK Control #ML0037
6
Rev 1.0
March 31, 2006