U630H16P Datasheet, PDF (15/17 Pages) Simtek Corporation – HardStore 2K x 8 nvSRAM

U630H16P
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence. It is not
necessary that G is LOW for the sequence to be valid.
After the t_STORE cycle time has been fulfilled, the SRAM
will again be activated for READ and WRITE operation.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1. Read address 000 (hex) Valid READ
2. Read address 555 (hex) Valid READ
3. Read address 2AA (hex) Valid READ
4. Read address 7FF (hex) Valid READ
5. Read address 0F0 (hex) Valid READ
6. Read address 70E (hex) Initiate RECALL
Hardware Protection
The U630H16P offers two levels of protection to sup-
press inadvertent STORE cycles. If the control signals
(E, G, W and NE) remain in the STORE condition at the
end of a STORE cycle, a second STORE cycle will not
be started. The STORE (or RECALL) will be initiated
only after a transition on any one of these signals to the
required state. In addition to multi-trigger protection, the
U630H16P offers hardware protection through V_CC
Sense. When V_CC < V_SWITCH the externally initiated
STORE operation will be inhibited.
Low Average Active Power
The U630H16P has been designed to draw signifi-
cantly less power when E is LOW (chip enabled) but
the access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
Automatic Power Up RECALL
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the V_CC level
On power up, once V_CC exceeds the sense voltage of
V_SWITCH, a RECALL cycle is automatically initiated. The
voltage on the V_CC pin must not drop below V_SWITCH
once it has risen above it in order for the RECALL to
operate properly. Due to this automatic RECALL,
SRAM operation cannot commence until t_RESTORE after
V_CC exceeds V_SWITCH. If the U630H16P is in a WRITE
state at the end of power up RECALL, the SRAM data
will be corrupted.
To help avoid this situation, a 10 KΩ resistor should be
connected between W and system V_CC.
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
March 31, 2006
STK Control #ML0037
15
Rev 1.0