ISL28025 Datasheet, PDF (9/48 Pages) Intersil Corporation – Precision Digital Power Monitor with Real Time Alerts

ISL28025
Electrical Specifications T_A = +25°C, I2CVCC = V_CC = 3.3V, V_INP = V_BUS = 12V, V_SENSE = V_INP - V_INM = 80mV, Aux V = 3V, Conversion
Time: Aux = Primary = 2.05ms, Internal AVG Aux = Primary = 128, unless otherwise specified. All voltages with respect to GND pin. Temperature limits
established by characterization. (Continued)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
MAX
(Note 6)
TYP
(Note 6) UNIT
TEMPERATURE SENSOR
Temperature Sensor Measurement Range
-40
125
°C
Temperature Accuracy
T = +25°C
+3.2
°C
Temperature Resolution
0.5
°C
Measurement Time
SMBus/I²C INTERFACE SPECIFICATIONS
0.5
ms
V_IL
SMBDAT and SMBCLK Input Buffer Low
Voltage
-0.3
0.3 x
V
I2CVCC
V_IH
SMBDAT and SMBCLK Input Buffer High
Voltage
0.7 x
I2CVCC
I2CVCC +
V
0.3
Hysteresis SMBDAT and SMBCLK Input Buffer
Hysteresis
0.05 x
V
I2CVCC
V_OL
SMBDAT Output Buffer Low Voltage,
I2CVCC = 5V, I_OL = 3mA
Sinking 3mA
0
0.02
0.4
V
C_PIN
f_SMBCLK
t_IN
SMBDAT and SMBCLK Pin Capacitance
SMBCLK Frequency
T_A = +25°C, f = 1MHz, I2CVCC = 5V,
V_IN = 0V, V_OUT = 0V
Pulse Width Suppression Time at SMBDAT Any pulse narrower than the max spec
and SMBCLK Inputs
is suppressed
10
pF
400
kHz
50
ns
t_AA
SMBCLK Falling Edge to SMBDAT Output SMBCLK falling edge crossing 30% of
Data Valid
I2CVCC, until SMBDAT exits the 30% to
70% of I2CVCC window
900
ns
t_BUF
Time the Bus Must be Free Before the SMBDAT crossing 70% of I2CVCC
1300
ns
Start of a New Transmission
during a STOP condition, to SMBDAT
crossing 70% of I2CVCC during the
following START condition
t_LOW
Clock Low Time
Measured at the 30% of I2CVCC
1300
ns
crossing
t_HIGH
Clock High Time
Measured at the 70% of I2CVCC
600
ns
crossing
t_SU:STA START Condition Set-Up Time
SMBCLK rising edge to SMBDAT falling 600
ns
edge. Both crossing 70% of I2CVCC
t_HD:STA START Condition Hold Time
From SMBDAT falling edge crossing
600
ns
30% of I2CVCC to SMBCLK falling edge
crossing 70% of I2CVCC
t_SU:DAT Input Data Set-Up Time
From SMBDAT exiting the 30% to 70%
100
ns
of V_CC window, to SMBCLK rising edge
crossing 30% of I2CVCC
t_HD:DAT Input Data Hold Time
From SMBCLK falling edge crossing
20
30% of I2CVCC to SMBDAT entering the
30% to 70% of I2CVCC window
900
ns
t_SU:STO STOP Condition Set-Up Time
From SMBCLK rising edge crossing
600
ns
70% of I2CVCC, to SMBDAT rising edge
crossing 30% of I2CVCC
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9
FN8388.4
February 19, 2016