ISL28025 Datasheet, PDF (33/48 Pages) Intersil Corporation – Precision Digital Power Monitor with Real Time Alerts

ISL28025
UV_EN D[0]
The UV_EN enable bit controls the power to the undervoltage DAC
and comparator. Setting the bit to 1 enables the undervoltage
circuitry.
0XDE FORCE FEED-THROUGH ALERT REGISTER (R/W)
The Force Feed-through Alert Register is a read/writable byte
register that controls the polarity of the interrupt. The definition
of the control bits within the Force Feed-through Alert register is
defined in Table 34.
TABLE 34. 0xDE FORCE FEED-THROUGH ALERT REGISTER DEFINITION
BIT
NUMBER D[7:4]
D[3]
D[2]
D[1]
D[0]
Bit Name N/A A2POL A1POL FORCE A2 FORCE A1
Default 0000
0
0
0
0
Value
A2POL D[3], A2POL D[2]
The AxPOL bits control the polarity of an interrupt. A2POL bit
defines the SMBALERT2 pin active interrupt state. A1POL bit
defines the SMBALERT1 pin active interrupt state. Table 35
defines the functionality of the bit.
TABLE 35. AxPol BIT DEFINED
A2POL D[3], A1POL D[2]
INTERRUPT
ACTIVE STATE
0
low
1
high
FORCEA2 D[1], FORCEA1 D[0]
The FORCEAx bits allow the user to force an interrupt by setting
the bit. FORCEA2 bit controls the SMBALERT2 pin state.
FORCEA1 bit controls the SMBALERT1 pin state. Table 36 defines
the functionality of the bit.
TABLE 36. FORCEAx BIT DEFINED
FORCEA2 D[1], FORCEA1 D[0]
INTERRUPT
STATUS
0
Normal
1
Interrupt Forced
0X03 CLEAR FAULTS (S)
The Clear Faults register is a send byte command that clears all
faults pertaining to the status registers. Upon execution of the
command, the status registers returns to the default state
defined in Table 2 on page 22.
0X7A STATUS V_OUT (R/W)
The Status V_OUT register is a read/writable byte register that
reports over and undervoltage warnings for the V_BUS input.
TABLE 37. 0x7A STATUS V_OUT REGISTER DEFINITION
BIT NUMBER D[7]
D[6]
D[5]
D[4:0]
Bit Name
N/A
V_OUT OV
V_OUT UV
N/A
Warning
Warning
Default
0
0
Value
0
0 0000
V_OUT OV WARNING D[6]
The V_OUT OV Warning bit is set to 1 when an overvoltage fault
occurs on the V_BUS input. The V_BUS overvoltage threshold is set
from the V_OUT OV Threshold Set register. In the event of a V_BUS
overvoltage condition, the V_OUT OV Warning is latched to 1.
Writing a 1 to the V_OUT OV Warning bit will clear the warning
resulting in a bit value equal to 0.
VOUT UV WARNING D[5]
The V_OUT UV Warning bit is set to 1 when an undervoltage fault
occurs on the V_BUS input. The V_BUS undervoltage threshold is set
from the V_OUT UV Threshold Set register. In the event of a V_BUS
undervoltage condition, the V_OUT UV Warning is latched to 1.
Writing a 1 to the V_OUT UV Warning bit will clear the warning
resulting in a bit value equal to 0.
0X7B STATUS I_OUT (R/W)
The Status I_OUT register is a read/writable byte register that
reports an overcurrent warning for the V_SHUNT input.
TABLE 38. 0x7B STATUS I_OUT REGISTER DEFINITION
BIT NUMBER D[7]
D[6]
D[5]
D[4:0]
Bit Name
N/A
N/A
I_OUT OC
N/A
Warning
Default
0
0
Value
0
0 0000
I_OUT OC WARNING D[5]
The I_OUT OC Warning bit is set to 1 when an overcurrent fault
occurs on the V_SHUNT input. The V_SHUNT overcurrent threshold is
set from the I_OUT OC Threshold Set register. In the event of a
V_SHUNT overcurrent condition, the I_OUT OC Warning is latched
to 1. Writing a 1 to the I_OUT OC Warning bit will clear the warning
resulting in a bit value equal to 0.
0X7D STATUS TEMPERATURE (R/W)
The Status Temperature register is a read/writable byte register
that reports an over-temperature warning initiated from the
internal temperature sensor.
TABLE 39. 0x7D STATUS TEMPERATURE REGISTER DEFINITION
BIT NUMBER D[7]
D[6]
D[5]
D[4:0]
Bit Name
N/A
OT
N/A
N/A
Warning
Default
0
0
Value
0
0 0000
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FN8388.4
February 19, 2016