ISL28025 Datasheet, PDF (26/48 Pages) Intersil Corporation – Precision Digital Power Monitor with Real Time Alerts

ISL28025
POST TRIGGER STATE D[4]
Data Bit 4 of the Set DPM Mode register controls the post ADC
state once an acquisition has been made in the trigger mode.
TABLE 11. 0xD2 SET DPM MODE REGISTER BIT 4 DEFINED
D4
ADC TRIGGER STATE
0
Idle Mode after a Trigger Measurement
1
PD Mode after Trigger Measurement
ADC MODE TYPE D[3]
Data Bit 3 of the Set DPM Mode register controls the behavior of
the ADC to either triggered or continuous. The continuous mode
has the ADC continuously acquiring data in a systematic manor
described by data bits [2:0] in the SET DPM MODE register. The
triggered mode instructs the ADC to make an acquisition
described by data bits [2:0]. The beginning of a triggered cycle
starts once writing to the Set DPM Mode register commences.
The trigger mode is useful for reading a single measurement per
acquisition cycle.
TABLE 12. 0xD2 SET DPM MODE REGISTER BIT 3 DEFINED
D3
ADC MODE TYPE
0
Trigger
1
Continuous
OPERATING MODE D[2:0]
The Operating Mode bits of the Set DPM Mode register control
the state machine within the chip. The state machine globally
controls the overall functionality of the chip. Table 13 shows the
various measurement states the chip can be configured to, as
well as the mode bit definitions to achieve a desired
measurement state. The shaded row is the default setting upon
power-up.
TABLE 13. 0xD2 SET DPM MODE REGISTER BITS 2 TO 0 DEFINED
D[2:0]
MEASUREMENT INPUT
0
Primary Channel Shunt Voltage
1
Primary Channel V_BUS Voltage
2
Primary Shunt and V_BUS Voltages
3
Do Not Select
4
Auxiliary Channel V_BUS Voltage
5
Do Not Select
6
Internal Temperature
7
All
0XD3 DPM CONVERSION STATUS (R)
The DPM conversion status register is a readable byte register
that reports the status of a conversion when the DPM is
programmed in the trigger mode.
TABLE 14. 0xD3 DPM CONVERSION STATUS REGISTER DEFINITION
BIT NUMBER
D[7:2]
D[1]
D[0]
Bit Name
N/A
CNVR
OVF
Default
0
0
0
Value
CNVR: CONVERSION READY D[1]
The Conversion Ready bit indicates when the ADC has finished a
conversion and has transferred the reading(s) to the appropriate
register(s). The CNVR is only operable when the ADC state is set
to trigger. The CNVR is in a low state when the conversion is in
progress. When the CNVR bit transitions from a low state to a
high state and remains at a high state, the conversion is
complete. The CNVR initializes or reinitializes when writing to the
Set DPM Mode register.
OVF: MATH OVERFLOW FLAG D[0]
The Math Overflow Flag (OVF) bit is set to indicate the current and
power data being read from the DPM is overranged and
meaningless.
0XD4 CONFIGURE I_CHANNEL (R/W)
The Configure I_CHANNEL register is a read/writable word register
that configures the ADC measurement acquisition settings for
the primary and auxiliary voltage shunt inputs.
TABLE 15. 0xD4 CONFIGURE I_CHANNEL REGISTER DEFINITION
BIT
NUMBER D[15:7] D[13:10] D[9:7]
D[6:3]
D[2:0]
Bit
N/A
N/A
N/A
Primary Primary
Name
Shunt
Shunt
Sample Conversion
AVG
Time
Default
00
00 00
11 1
000 0
111
Value
SHUNT VOLTAGE CONVERSION TIME D[2:0]
The Shunt Voltage Conversion Time bits set the acquisition speed
of the ADC when measuring the primary voltage shunt channel of
the DPM. The primary voltage shunt channel has independent
timing control bits allowing for the primary voltage shunt channel
to have a unique acquisition time with the respect to other
channels within the DPM. Table 16 is a list of the selectable
voltage shunt ADC time settings. The shaded row indicates the
default setting.
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FN8388.4
February 19, 2016