ISL28025 Datasheet, PDF (40/48 Pages) Intersil Corporation – Precision Digital Power Monitor with Real Time Alerts

External Clock
VIN = 4.5VÆ 36V
ISL28025
ISL28025
VINP
3.3V
Vreg
VIN
ISL85415
VOUT =
0.6 * (1+ R2/R1)
PHASE
Lo
0.1µF
VINM
VBUS
AuxV
SYNC
BOOT
VIN
PG
En
FB
SMBALERT1
EXT CLK
VIN
To ISL85415 SYNC
GPIO
GPIO
ADC
16-Bit
PMBus
REG
MAP
TEMP
SENSE
MCU
GPIO/Int
SCL
SDA
VCC
GND
A0
A1
A2
SCL
SDA
I2CVCC
FIGURE 77. SIMPLIFIED SCHEMATIC OF THE ISL28025
SYNCHRONIZED TO A MCU SYSTEM CLOCK
An externally controlled clock allows measurements to be
synchronized to an event that is time dependent. The event could
be application generated, such as timing a current measurement
to a charging capacitor in a switch regulator application or the
event could be environmental. A voltage or current measurement
may be susceptible to crosstalk from a controlled source. Instead
of filtering the environmental noise from the measurement,
another approach would be to synchronize the measurement to
the source. The variability and accuracy of the measurement will
improve.
The ISL28025 has the functionality to allow for synchronization
to an external clock. The speed of the external clock combined
with the choice of the internal chip frequency division value
determines the acquisition times of the ADC. The internal system
clock frequency is 500kHz. The internal system clock is also the
ADC sampling clock. The acquisition times scale linearly from
500kHz. For example, an external clock frequency of 4.0MHz
with a frequency divide setting of 0 (internal divide by 8) results
in acquisition times that equals the internal oscillator frequency
when enabled. The ADC modulator is optimized for frequencies
of 500kHz. Operating internal clock frequencies beyond 500kHz
may result in measurement accuracy errors due to the modulator
not having enough time to settle.
Suppose an external clock frequency of 5.5MHz is applied with a
divide by 88 internal frequency setting, the system clock speed is
62.5kHz or 8x slower than internal system clock. The acquisition
times for this example will increase by 8. For a channel’s
conversion time setting of 2.048ms, the ISL28025 will have an
acquisition time of 256µs.
FIGURE 78. EXTERNAL CLOCK MODE
Figure 78 illustrates a simple mathematical diagram of the ECLK
pin internal connection. The external clock divide is controlled by
way of the EXTCLKDIV bit in register 0xE5.
0.5
-1.5
-3.5
-5.5
ExtClkDiv = 3
ExtClkDiv = 4
-7.5
ExtClkDiv = 14
-9.5
ExtClkDiv = 0
ExtClkDiv = 1
-11.5 ^{FreqExtClk = 16MHz}
ADC TIME SETTING
-13.5 ^{(CONFIG_ICHANNEL) = 0}
-15.5
10
100
1k
10k
FREQUENCY (Hz)
FIGURE 79. MEASUREMENT BANDWIDTH vs EXTERNAL CLK
FREQUENCY
100k
Figure 79 illustrates how changing the system clock frequency
effects the measurement bandwidth (the ADC acquisition time).
The bandwidth of the external clock circuitry is 25MHz. Figure 80
shows the bandwidth of the external clock circuitry when the
external clock division bits equals to 0.
The external clock pin can accept signal frequencies above
25MHz by programming the system clock frequency, such that
the internal clock frequency is below 25MHz.
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FN8388.4
February 19, 2016