SI5322 Datasheet, PDF (8/16 Pages) Silicon Laboratories – PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Si5322
Pin #
21
23
22
27
26
25
24
33
30
Pin Name
CS_CA
BWSEL1
BWSEL0
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
SFOUT0
SFOUT1
Table 3. Si5322 Pin Descriptions (Continued)
I/O Signal Level
Description
Input Clock Select/Active Clock Indicator.
If manual clock selection mode is chosen (AUTOSEL = L),
this pin functions as the manual input clock selector. This
input is internally deglitched to prevent inadvertent clock
switching during changes in the CS input state.
0 = Select CKIN1.
1 = Select CKIN2.
I/O LVCMOS _{If automatic clock selection mode is chosen (AUTOSEL = M}
or H), this pin indicates which of the two input clocks is cur-
rently the active clock. If alarms exist on both CKIN1 and
CKIN2, indicating that the digital hold state has been
entered, CA will indicate the last active clock that was used
before entering the hold state.
0 = CKIN1 active input clock.
1 = CKIN2 active input clock.
Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
I
3-Level _{width. Detailed operations and timing characteristics for}
these pins may be found in the Any-Rate Precision Clock
Family Reference Manual.
Multiplier Select.
Three level inputs that select the input clock and clock multi-
I
3-Level ^{plication ratio, depending on the FRQTBL setting. Consult}
the Any-Rate Precision Clock Family Reference Manual or
DSPLLsim configuration software for settings, both avail-
able for download at www.silabs.com/timing.
Signal Format Select.
Three level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2. Valid settings include LVPECL, LVDS, and
CML. Also includes selections for CMOS mode, tristate
mode, and tristate/sleep mode.
I
3-Level
SFOUT[1:0]
HH
HM
HL
MH
MM
ML
LH
LM
LL
Signal Format
Reserved
Reserved
CML
LVPECL
Reserved
LVDS
CMOS
Tristate/Sleep
Reserved
8
Preliminary Rev. 0.47