SI5322 Datasheet, PDF (1/16 Pages) Silicon Laboratories – PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Si5322
PRELIMINARY DATA SHEET
PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
Description
The Si5322 is a low jitter, precision clock multiplier for
high-speed communication systems, including SONET
OC-48/OC-192, Ethernet, and Fibre Channel. The
Si5322 accepts dual clock inputs ranging from 19.44 to
707 MHz and generates two equal frequency-
multiplied clock outputs ranging from 19.44 to
1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of
popular SONET, Ethernet, and Fibre Channel rates.
The Si5322 is based on Silicon Laboratories' 3rd-
generation DSPLL^® technology, which provides any-
rate frequency synthesis in a highly integrated PLL
solution that eliminates the need for external VCXO
and loop filter components. The DSPLL loop bandwidth
is digitally programmable, providing jitter performance
optimization at the application level. Operating from a
single 1.8, 2.5, or 3.3 V supply, the Si5322 is ideal for
providing clock multiplication in high performance
timing applications.
Applications
„ SONET/SDH OC-48/OC-192 line cards
„ GbE/10GbE, 1/2/4/8/10GFC line cards
„ ITU G.709 line cards
„ Optical modules
„ Test and measurement
Features
„ Selectable output frequencies ranging from 19.44 to
1050 MHz
„ Low jitter clock outputs with jitter generation as low
as 0.6 ps_RMS (50 kHz–80 MHz)
„ Integrated loop filter with selectable loop bandwidth
(30 kHz to 1.3 MHz)
„ Dual clock inputs with manual or automatically
controlled hitless switching
„ Dual clock outputs with selectable signal format:
LVPECL, LVDS, CML, CMOS
„ Support for ITU G.709 FEC ratios (255/238,
255/237, 255/236)
„ LOS alarm output
„ Pin-controlled output phase adjust
„ Pin-programmable settings
„ On-chip voltage regulator for 1.8, 2.5, or 3.3 V
±10% operation
„ Small size: 6 x 6 mm 36-lead QFN
„ Pb-free, RoHS compliant
CKIN1
CKIN2
DSPLL^®
Loss of Signal
Signal Detect
Control
Frequency Select
Bandwidth Select
Manual/Auto Switch
Clock Select
CKOUT1
Signal Format
CKOUT2
Disable/BYPASS
VDD (1.8, 2.5, or 3.3 V)
GND
Preliminary Rev. 0.47 7/07
Copyright © 2007 by Silicon Laboratories
Si5322
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.