EZR32LG330 Datasheet, PDF (71/87 Pages) Silicon Laboratories – Building and home automation

5.2 Pin Descriptions
EZR32LG330 Data Sheet
Pinout and Package
Table 5.1. Device Pinout
QFN64 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
0
VSS
Ground.
1
NC
No connect.
2
RXP
Differential RF Input Pin of the LNA. See application schematic for example matching network.
3
RXN
Differential RF Input Pin of the LNA. See application schematic for example matching network.
Transmit Output Pin (+13 dBm or +16 dBm) for R55, R60, R61, R67 and R69 variants. The PA output is
4
TX_13/16
an open-drain connection, so the L-C match must supply VDD (+3.3 VDC nominal) to this pin. Pin is DNC
on the +20 dBm parts.
Transmit Output Pin (+20 dBm) for R63, R68 and R69 variants. The PA output is an open-drain connec-
5
TX_20
tion, so the L-C match must supply VDD (+3.3 VDC nominal) to this pin. Pin is DNC on the +13 dBm
parts.
6
NC
No connect.
7
RFVDD_2
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators for the Radio. The recommended VDD supply
voltage is +3.3 V.
8
TXRAMP
Programmable Bias Output with Ramp Capability for External FET PA.
9
RFVDD_1
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators for the Radio. The recommended VDD supply
voltage is +3.3 V.
10
PA0¹
TIM0_CC0 #0/1/4
LEU0_RX #4 I2C0_SDA
#0
PRS_CH0 #0
GPIO_EM4WU0
RF_GPIO0
11
PA1 ¹
TIM0_CC1 #0/1
I2C0_SCL #0
CMU_CLK1 #0
PRS_CH1 #0
RF_GPIO1
12
IOVDD_0
Digital IO power supply 0.
13
PB3
PCNT1_S0IN #1
US2_TX #1
14
PB4
PCNT1_S1IN #1
US2_RX #1
15
PB5
US2_CLK #1
16
PB6
US2_CS #1
17
PB7
LFXTAL_P
TIM1_CC0 #3
USRF0_TX #4
18
PB8
LFXTAL_N
TIM1_CC1 #3
USRF0_RX #4
19
PA12
TIM2_CC0 #1
20
PA13
TIM2_CC1 #1
21
PA14
TIM2_CC2 #1
22
RESETn
Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
23
PB11
TIM1_CC2 #3 LE-
TIM0_OUT0 #1
24
AVDD_1
Analog power supply 1.
25
PB13
HFXTAL_P
LEU0_TX #1
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