SI597 Datasheet, PDF (7/12 Pages) Silicon Laboratories – QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL

Si597
3. Ordering Information
The Si597 supports a variety of options including frequency, temperature stability, tuning slope, output format, and
V_DD. Specific device configurations are programmed into the Si597 at time of shipment. Configurations are
specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part
number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool
and for further ordering instructions. The Si597 VCXO series is supplied in an industry-standard, RoHS compliant,
lead-free, 8-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
597
X
X
XXXXXX
D
G
R
597 Quad VCXO
Product Family
R = Tape & Reel
Blank = Trays
Operating Temp Range (°C)
G
–40 to +85 °C
Device Revision Letter
1^st Option Code
V_DD Output Format Output Enable Polarity
A 3.3 LVPECL
High
B 3.3 LVDS
High
C 3.3 CMOS
High
D 3.3 CML
High
E 2.5 LVPECL
High
F 2.5 LVDS
High
G 2.5 CMOS
High
H 2.5 CML
High
J 1.8 CMOS
High
K 1.8 CML
High
M 3.3 LVPECL
Low
N 3.3 LVDS
Low
P 3.3 CMOS
Low
Q 3.3 CML
Low
R 2.5 LVPECL
Low
S 2.5 LVDS
Low
T 2.5 CMOS
Low
U 2.5 CML
Low
V 1.8 CMOS
Low
W 1.8 CML
Low
Note:
CMOS available to 160 MHz.
6-digit Frequency Designator Code
Four unique frequencies can be specified within the following
frequency range: 10 to 810 MHz. A six digit code will be assigned for
the specified combination of frequencies. Codes > 000100 refer to
VCXOs programmed with the lowest frequency value selected when
FS[1:0] = 00, and the highest value when FS[1:0] = 11. Six digit codes
< 000100 refer to VCXOs programmed with the highest frequency
value selected when FS[1:0] = 00, and the lowest value when FS[1:0]
= 11.
2^nd Option Code
Code
A
B
C
D
E
F
G
H
Temperature
Stability
± ppm (max)
20
20
50
20
20
50
50
20
Tuning Slope
Kv
ppm/V (typ)
380
185
185
125
95
125
95
45
Minimum APR
(±ppm) for VDD @
3.3 V
2.5 V
1.8 V
370
275
200
160
110
80
130
80
50
100
75
40
65
50
25
70
45
10
35
20
N/A
15
N/A
N/A
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Lower Kv options minimize noise
coupling and jitter in real-world PLL designs. See AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±100 ppm is able to lock to a clock with a ±100 ppm stability over 15 years over
all operating conditions.
3. Nominal Pull range (±) = 0.5 x V_DD x tuning slope.
4. Minimum APR values noted above include worst case values for all parameters.
Figure 1. Part Number Syntax
Rev. 1.0
7