SI597 Datasheet, PDF(3/12 Page) Silicon Laboratories – QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL

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SI597 Datasheet, PDF (3/12 Pages) Silicon Laboratories – QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL

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Si597

Table 3. CLKÂ± Output Frequency Characteristics

Parameter

Symbol

Test Condition

Min

Nominal Frequency1,2,3

LVDS/CML/LVPECL

CMOS

Temperature Stability1,4

TA = â40 to +85 ÂºC

â20

â50

Absolute Pull Range1,4

APR

VDD = 3.3 V

Â±15

Power up Time5

tOSC

Notes:

1. See Section 3. "Ordering Information" on page 7 for further details.

2. Specified at time of order by part number.

3. Nominal output frequency set by VCNOM = VDD/2.

4. Selectable parameter specified by part number. See âOrdering Informationâ.

5. Time from power up or tristate mode to fO.

Typ

Max Unit

810 MHz

160 MHz

+20 ppm

+50 ppm

Â±370 ppm

Table 4. CLKÂ± Output Levels and Symmetry

Parameter

LVPECL Output Option1

LVDS Output Option2

Symbol

VOD

VSE

Test Condition

mid-level

swing (diff)

swing (single-ended)

mid-level

Min

VDD â 1.42

1.1

0.55

1.125

Typ

1.20

Max Unit

VDD â 1.25 V

1.9

VPP

0.95

VPP

1.275

VOD

swing (diff)

0.5

0.7

0.9

VPP

CML Output Option2

2.5/3.3 V option mid-level

VDD â 1.30

1.8 V option mid-level

VDD â 0.36

VPP

VOD 2.5/3.3 V option swing (diff)

1.10

1.50

1.90

CMOS Output Option3

1.8 V option swing (diff)

0.35

0.425

0.50

VPP

VOH

0.8 x VDD

VDD

VOL

0.4

Rise/Fall time (20/80%)

tR, tF

LVPECL/LVDS/CML

350

CMOS with CL = 15 pF

Symmetry (duty cycle)

SYM LVPECL: VDD â 1.3 V (diff)

LVDS: 1.25 V (diff)

CMOS: VDD/2

Notes:

1. 50 ï to VDD â 2.0 V.

2. Rterm = 100 ï (differential).

3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD = 1.8 V.

Rev. 1.0

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