SI597 Datasheet, PDF (4/12 Pages) Silicon Laboratories – QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL

Si597
Table 5. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)^1,2
for F_OUT of 50 MHz < F_OUT <
810 MHz
Symbol
_J
Test Condition
Kv = 45 ppm/V
12 kHz to 20 MHz
Kv = 95 ppm/V
12 kHz to 20 MHz
Min
Typ
Max Unit
—
0.5
—
ps
—
0.5
—
ps
Kv = 125 ppm/V
12 kHz to 20 MHz
—
0.5
—
ps
Kv = 185 ppm/V
12 kHz to 20 MHz
—
0.5
—
ps
Kv = 380 ppm/V
12 kHz to 20 MHz
—
0.7
—
ps
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN256 and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest K_V that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.
Table 6. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Period Jitter*
J_PER
RMS
Peak-to-Peak
—
3
—
ps
—
35
—
ps
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 7. CLK± Output Phase Noise (Typical)
Offset Frequency
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
74.25 MHz
185 ppm/V
LVPECL
–77
–101
–121
–134
–149
–151
–150
148.5 MHz
185 ppm/V
LVPECL
–68
–95
–116
–128
–144
–147
–148
155.52 MHz
95 ppm/V
LVPECL
–77
–101
–119
–127
–144
–147
–148
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
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Rev. 1.0