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SI595 Datasheet, PDF (7/12 Pages) Silicon Laboratories – VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR
Si595
3. Ordering Information
The Si595 supports a variety of options including frequency, temperature stability, tuning slope, output format, and
VDD. Specific device configurations are programmed into the Si595 at time of shipment. Configurations are
specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part
number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool
and for further ordering instructions. The Si595 VCXO series is supplied in an industry-standard, RoHS compliant,
lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
595
X
X
XXXMXXX
D
G
R
595 VCXO
Product Family
R = Tape & Reel
Blank = Trays
Operating Temp Range (°C)
G
–40 to +85 °C
Device Revision Letter
1st Option Code
VDD Output Format Output Enable Polarity
A 3.3 LVPECL
High
B 3.3 LVDS
High
C 3.3 CMOS
High
D 3.3 CML
High
E 2.5 LVPECL
High
F 2.5 LVDS
High
G 2.5 CMOS
High
H 2.5 CML
High
J 1.8 CMOS
High
K 1.8 CML
High
M 3.3 LVPECL
Low
N 3.3 LVDS
Low
P 3.3 CMOS
Low
Q 3.3 CML
Low
R 2.5 LVPECL
Low
S 2.5 LVDS
Low
T 2.5 CMOS
Low
U 2.5 CML
Low
V 1.8 CMOS
Low
W 1.8 CML
Low
Note:
CMOS available to 160 MHz.
Frequency (e.g., 148M500 is 148.5 MHz)
Available frequency range is 10 to 810 MHz. The position of “M” shifts
to denote higher or lower frequencies. If the frequency of interest
requires greater than 6 digit resolution, a six digit code will be
assigned for the specific frequency.
2nd Option Code
Code
A
B
C
D
E
F
G
H
Temperature
Stability
± ppm (max)
20
20
50
20
20
50
50
20
Tuning Slope
Kv
ppm/V (typ)
380
185
185
125
95
125
95
45
Minimum APR
(±ppm) for VDD @
3.3 V
2.5 V
1.8 V
370
275
200
160
110
80
130
80
50
100
75
40
65
50
25
70
45
10
35
20
N/A
15
N/A
N/A
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Lower Kv options minimize noise
coupling and jitter in real-world PLL designs. See AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±100 ppm is able to lock to a clock with a ±100 ppm stability over 15 years over
all operating conditions.
3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.
4. Minimum APR values noted above include worst case values for all parameters.
Example Part Number: 595AE148M500DGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 148.5 MHz, with a 3.3 V supply,
LVPECL output, and Output Enable active high polarity. Temperature stability is specified as ±20 ppm and the tuning slope is 95 ppm/V. The part is
specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.
Figure 1. Part Number Convention
Rev. 1.2
7