SI595 Datasheet, PDF (3/12 Pages) Silicon Laboratories – VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR

Si595
Table 3. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency^1,2,3
Temperature Stability^1,4
Symbol
f_O
Test Condition
LVDS/CML/LVPECL
CMOS
T_A = –40 to +85 ºC
Absolute Pull Range^1,4
APR
Power up Time⁵
t_OSC
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number.
3. Nominal output frequency set by V_CNOM = V_DD/2.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to f_O.
Min
Typ
Max Units
10
—
810
MHz
10
—
160
–20
–50
—
—
+20
+50
ppm
±10
—
±370 ppm
—
—
10
ms
Table 4. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option¹
LVDS Output Option²
Symbol
V_O
V_OD
V_SE
V_O
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
Min
V_DD – 1.42
1.1
0.55
1.125
Typ
—
—
—
1.20
Max Units
V_DD – 1.25 V
1.9
V_PP
0.95
V_PP
1.275
V
V_OD
swing (diff)
0.5
0.7
0.9
V_PP
CML Output Option²
2.5/3.3 V option mid-level
V_O
1.8 V option mid-level
—
V_DD – 1.30
—
—
V_DD – 0.36
—
V
2.5/3.3 V option swing (diff) 1.10
V_OD
1.8 V option swing (diff)
0.35
1.50
0.425
1.90
0.50
V_PP
CMOS Output Option³
V_OH
V_OL
0.8 x V_DD
—
—
—
V_DD
V
0.4
Rise/Fall time (20/80%)
t_R, t_F
LVPECL/LVDS/CML
—
—
350
ps
CMOS with C_L = 15 pF
—
2
—
ns
Symmetry (duty cycle)
SYM LVPECL: V_DD – 1.3 V (diff)
LVDS: 1.25 V (diff)
45
—
55
%
CMOS: V_DD/2
Notes:
1. 50  to V_DD – 2.0 V.
2. R_term = 100  (differential).
3. C_L = 15 pF. Sinking or sourcing 12 mA for V_DD = 3.3 V, 6 mA for V_DD = 2.5 V, 3 mA for V_DD = 1.8 V.
Rev. 1.2
3