SI51210 Datasheet, PDF (7/12 Pages) Silicon Laboratories – TWO OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR

Si51210
3. Functional Description
3.1. Input Frequency Range
The input frequency range is from 8.0 to 48.0 MHz for crystals and ceramic resonators. If an external clock is used,
the input frequency range is from 8.0 to 166.0 MHz.
3.2. Output Frequency Range and Outputs
Up to two outputs can be programmed as SSCLK or REFCLK. SSCLK output can be synthesized to any value from
3 to 200 MHz with spread based on valid input frequency. The spread at SSCLK pins can be stopped by the SSON
input control pin. If SSON pin is high (VDD), the frequency at SSCLK pin is synthesized to the nominal value of the
input frequency and there is no spread.
REFCLK is the buffered output of the oscillator and is the same frequency as the input frequency without spread.
However, REFCLK_D output is divided by output dividers from 2 to 32. By using only low cost, fundamental mode
crystals, the Si51210 can synthesize output frequency up to 200 MHz, eliminating the need for higher order
crystals (Xtals) and crystal oscillators (XOs). This reduces the cost while improving the system clock accuracy,
performance, and reliability
3.3. Programmable Modulation Frequency
The spread spectrum clock (SSC) modulation default value is 31.5 kHz. The higher values of up to 62 kHz can also
be programmed. Less than 30 kHz modulation frequency is not recommended to stay out of the range audio
frequency bandwidth since this frequency could be detected as a noise by the audio receivers within the vicinity.
3.4. Programmable Spread Percent (%)
The spread percent (%) value is programmable from ±0.25% to ±1% (center spread) for all SSCLK frequencies. It
is possible to program smaller or larger non-standard values of spread percentage. Contact Silicon Labs if these
non-standard spread percent values are required in the application.
3.5. SSON or Frequency Select (FSEL)
The Si51210 pin 4 and 5 can be programmed as either SSON to enable or disable the programmed spread percent
value or as frequency select (FSEL). If SSON is used, when this pin is pulled high (VDD), the spread is stopped
and the frequency is the nominal value without spread. If low (GND), the frequency is the nominal value with the
spread.
If FSEL function is used, the output pin can be programmed for different set of frequencies as selected by FSEL.
SSCLK value can be any frequency from 3 to 200 MHz, but the spread % is the same percent value. REFCLK is
the same frequency as the input reference clock and the REFCLK_D is input clock divided by 2 to 32 without spread. The
set of frequencies in Table 4 is given as an example, using a 48 MHz crystal.
Table 4. Example Frequencies
FSEL
(Pin 4)
0
SSCLK1
(Pin 5)
66 MHz, ±1%
1
33 MHz, ±1%
3.6. Power Down (PD) or Output Enable (OE)
The Si51210 pin 5 can be programmed as PD input. Pin 4 and pin 5 can be programmed as OE input. PD turns off
both PLL and output buffers whereas OE only disables the output buffers to Hi-Z.
Preliminary Rev. 0.7
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