SI51210 Datasheet, PDF (5/12 Pages) Silicon Laboratories – TWO OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR

Si51210
Table 2. AC Electrical Specifications
(V_DD = 2.5 V ±5%, or V_DD = 3.3 V ± 10%, T_A = 0 to 70 ^oC)
Parameter
Symbol
Condition
Min
Input Frequency Range
F_IN1
Crystal input
8
Input Frequency Range
F_IN2
Reference clock Input
3
Output Frequency Range
F_OUT
SSCLK1/2, CL=15 pF
3
Frequency Accuracy
F_ACC
Configuration dependent
—
Output Duty Cycle
DC_OUT
Measured at V_DD/2
45
Input Duty Cycle
DC_IN
CLKIN, CLKOUT through PLL
30
Output Rise Time
t_r
C_L=15 pF, 20 to 80%
—
Output Fall Time
t_f
C_L=15 pF, 20 to 80%
—
Period Jitter
PJ₁
SSCLK1/2, two clocks running,
—
V_DD=3.3 V, C_L=15 pF
Cycle-to-Cycle Jitter
CCJ₁
SSCLK1/2, two clocks running,
—
V_DD=3.3 V, C_L=15 pF
Power-up Time
t_PU
Time from 0.9 V_DD to valid
—
frequencies at all clock outputs
Output Enable Time
t_OE
Time from OE raising edge to active —
at output SSCLK (asynchronous)
Output Disable Time
t_OD Time from OE falling edge to active at —
output SSCLK (asynchronous)
*Note: Jitter performance depends on configuration and programming parameters.
Typ
—
—
—
0
50
50
1
1
150^*
100^*
1.2
15
15
Max Unit
48 MHz
166 MHz
200 MHz
— ppm
55 %
70 %
3.0 ns
3.0 ns
— ps
— ps
5.0 ms
— ns
— ns
Table 3. Absolute Maximum Conditions
Parameter
Main Supply Voltage
Input Voltage
Temperature,
Temperature, Operating Ambient
ESD Protection (Human Body Model)
ESD Protection (Charge Device Model)
ESD Protection (Machine Model)
Moisture Sensitivity Level
Symbol
V_DD
V_IN
T_S
T_A
ESD_HBM
ESD_CDM
ESD_MM
MSL
Condition
Min Typ Max Unit
–0.5 —
4.2
V
Relative to V_SS
Non-functional
–0.5
–65
— V_DD+0.5 V
—
150
°C
Functional, C-Grade
0
—
70
°C
JEDEC (JESD 22-A114) –4000 —
4000
V
JEDEC (JESD 22-C101) –1500 —
1500
V
JEDEC (JESD 22-A115) –200 —
200
V
JEDEC (J-STD-020)
1
Note: While using multiple power supplies, the Voltage on any input or I/O pin cannot exceed the power pin during power-up.
Power supply sequencing is not required.
Preliminary Rev. 0.7
5