SI51210 Datasheet, PDF (6/12 Pages) Silicon Laboratories – TWO OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR

Si51210
2. Design Considerations
2.1. Typical Application Schematic
0.1µF
VDD
10µF
VDD
VSS
CL1
XXOINUT
SSCLK3
Si51210
XXOINUT
FSEL
CL2
VDD
5K
5K
2.2. Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1 μF must be used between VDD and VSS on pin 1. Place the
capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin
and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the
VDD pin. In addition, a 10 µF capacitor should be placed between VDD and VSS.
Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs
(SSCLK or REFCLK pins) and the load is over 1 ½ inches. The nominal impedance of the SSCLK output is about
30 Ω. Use a 20 Ω resistor in series with the output to terminate a 50 Ω trace impedance and place a 20 Ω resistor
as close to the SSCLK output as possible.
Crystal and Crystal Load: Only use a parallel resonant fundamental AT cut crystal. Do not use higher overtone
crystals. To meet the crystal initial accuracy specification (in ppm) make sure that external crystal load capacitor is
matched to crystal load specification. To determine the value of CL1 and CL2, use the following formula:
C1 = C2 = 2CL – (Cpin + Cp)
Where: CL is load capacitance stated by crystal manufacturer
Cpin is the Si51210 pin capacitance (4 pF).
Cp is the parasitic capacitance of the PCB traces.
Example: If a crystal with CL = 12 pF specification is used and Cp = 1 pF (parasitic PCB capacitance on PCB), 19
or 20 pF external capacitors from pins XIN (pin 2) and XOUT (Pin 3) to VSS are required. Users must verify Cp
value.
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Preliminary Rev. 0.7