EFM32TG210 Datasheet, PDF (7/66 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

2.2 Configuration Summary
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The features of the EFM32TG210 is a subset of the feature set described in the EFM32TG Reference
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M3
DBG
MSC
DMA
RMU
EMU
CMU
WDOG
PRS
I2C0
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
DAC0
OPAMP
AES
GPIO
Configuration
Pin Connections
Full configuration
NA
Full configuration
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
Full configuration
NA
Full configuration
NA
Full configuration
NA
Full configuration
NA
Full configuration
CMU_OUT0, CMU_OUT1
Full configuration
NA
Full configuration
NA
Full configuration
I2C0_SDA, I2C0_SCL
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
Full configuration
LEU0_TX, LEU0_RX
Full configuration
TIM0_CC[2:0]
Full configuration
TIM1_CC[2:0]
Full configuration
NA
Full configuration
LET0_O[1:0]
Full configuration, 16-bit count register PCNT0_S[1:0]
Full configuration
ACMP0_CH[1:0], ACMP0_O
Full configuration
ACMP1_CH[7:5], ACMP1_O
Full configuration
NA
Full configuration
ADC0_CH[7:4]
Full configuration
DAC0_OUT[0], DAC0_OUTxALT
Not all pins available
Outputs: OPAMP_OUT0,
OPAMP_OUT0ALT,
OPAMP_OUT1ALT, OPAMP_OUT2,
Inputs: OPAMP_P1, OPAMP_N1,
OPAMP_P2
Full configuration
NA
24 pins
Available pins are shown in
Table 4.3 (p. 49)
2.3 Memory Map
The EFM32TG210 memory map is shown in Figure 2.2 (p. 8) , with RAM and Flash sizes for the
largest memory configuration.
2015-03-06 - EFM32TG210FXX - d0012_Rev1.40
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