EFM32TG210 Datasheet, PDF (49/66 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

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Alternate
Functionality 0
PRS_CH1
PA1
PRS_CH2
PC0
PRS_CH3
PC1
TIM0_CC0
PA0
TIM0_CC1
PA1
TIM0_CC2
PA2
TIM1_CC0
PC13
TIM1_CC1
PC14
TIM1_CC2
PC15
US0_CLK
PE12
US0_CS
PE13
1
PA0
PA1
PA2
PE10
PE11
PE12
US0_RX
PE11
LOCATION
2
3
4
5
PB7
PB8
PB11
PC15
PC14
PA0
PC0
PC1
PD6
PD7
PC13
PB13
PB14
PF0
PF1
PF2
PB13
PB14
PE12 PB8
PC1
US0_TX
US1_CLK
US1_CS
US1_RX
PE10
PB7
PB8
PC1
PE13 PB7
PC0
PF0
PF1
PD6
US1_TX
PC0
PD7
6
Description
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output
(MISO).
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG210 is shown in Table 4.3 (p. 49) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Port A
Port B
Port C
Port D
Port E
Port F
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
PA2 PA1 PA0
- PB14 PB13 - PB11 -
-
PB8 PB7
-
-
-
-
-
-
-
PC15 PC14 PC13 -
-
-
-
-
-
-
-
-
-
-
PC1 PC0
-
-
-
-
-
-
-
-
PD7 PD6 PD5 PD4
-
-
-
-
-
- PE13 PE12 PE11 PE10 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF2 PF1 PF0
4.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG210 is shown in Figure 4.2 (p. 50) .
2015-03-06 - EFM32TG210FXX - d0012_Rev1.40
49
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