SI8751 Datasheet, PDF (6/27 Pages) Silicon Laboratories – Digital CMOS input option

2.4 LED Emulator Input (Si8752 Only)
Si8751/52 Data Sheet
System Overview
Figure 2.8. Diode Emulator Model and I-V Curve
The Si8752 uses input current to achieve the development of power across the isolation barrier. Therefore, the more current provided to
the input, the more power is developed on the isolated side of the device. This translates into a faster turn on time of the external FET.
This benefit is limited to an input current of about 15 mA. Beyond that, increasing the input current has little effect on the switching time
of the external FET.
2.5 Output Description
The output of the Si875x device develops a positive voltage on the GATE pin with respect to the SOURCE pin. This voltage is used to
turn on a typical field effect transistor (FET). Because power is transmitted across the isolation barrier, no isolated supply is required.
This can be used to drive a FET configured as a switch for a dc load. It can also be used to drive a pair of FETs configured as a switch
for an ac load. See 3. Applications.
2.6 Miller Clamp
2.6.1 Miller Clamp Description
The Si875x devices provide a clamping device to prevent unintended turn on of the external FET when a high dV/dt is present on the
FET’s drain. To use this feature, a capacitor is connected between the drain(s) of the FET(s) and one of the MCAPx inputs. A sudden,
positive slope on this pin will cause the clamp device within the Si875x to activate and provide a low impedance path between the gate
and source pins. This will prevent the FET from being unintentionally turned on.
The Si875x device provides two miller clamp input pins. This allows for both FET’s to be protected from unintended turn on when the
device is used in an AC switch configuration. In this case each drain is connected to an MCAPx input through a capacitor.
Connection to a MCAPx pin, and use of the Miller Clamp feature, is optional. The device will function as expected if these pins are left
unconnected.
2.6.2 Sizing Miller Clamp Capacitors
The recommended value of the capacitor used to connect the drain of the external FET to the Si875x device is typically 10 pf. If the
application has a very large dV/dt and the clamp is not adequately keeping the external FET off, then this capacitor value can be in-
creased up to 100 pf. The voltage rating of the capacitor should be greater than or equal to the peak voltage expected at the drain of
the FET.
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