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SI52146 Datasheet, PDF (5/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 SIX OUTPUT CLOCK GENERATOR | |||
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Si52146
Table 2. AC Electrical Specifications
Parameter
Symbol
Condition
Crystal
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
CLKIN Rise and Fall Times
LACC
TDC
TR/TF
CLKIN Cycle to Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF at 0.7 V
DIFF Duty Cycle
Any DIFF Clock Skew from the
Earliest Bank to the Latest
Bank
TCCJ
TLTJ
VIH
VIL
IIH
IIL
TDC
TSKEW(win
dow)
Measured at VDD/2 differential
Measured at VDD/2
Measured between 0.2 VDD and
0.8 VDD
Measured at VDD/2
Measured at VDD/2
XIN/CLKIN pin
XIN/CLKIN pin
XIN/CLKIN pin, VIN = VDD
XIN/CLKIN pin, 0 < VIN <0.8
Measured at 0 V differential
Measured at 0 V differential
DIFF Cycle to Cycle Jitter
Output PCIe Gen1 REFCLK
Phase Jitter
TCCJ
RMSGEN1
Measured at 0 V differential
Includes PLL BW 1.5â22 MHz,
ζ = 0.54, Td=10 ns,
Ftrk=1.5 MHz with BER = 1E-12
Output PCIe Gen2 REFCLK
Phase Jitter
RMSGEN2 Includes PLL BW 8â16 MHz, Jitter
Peaking = 3 dB, ζ = 0.54,
Td=12 ns), Low Band, F < 1.5 MHz
Output PCIe Gen2 REFCLK
Phase Jitter
RMSGEN2
Includes PLL BW 8â16 MHz, Jitter
Peaking = 3 dB, ζ = 0.54,
Td=12 ns), High Band,
1.5 MHz < F < Nyquist
Output Phase Jitter Impactâ RMSGEN3
PCIe Gen3
Includes PLL BW 2â4 MHz,
CDR = 10 MHz)
DIFF Long Term Accuracy
DIFF Rising/Falling Slew Rate
LACC
TR/TF
Measured at 0 V differential
Measured differentially from
±150 mV
Voltage High
Voltage Low
Crossing Point Voltage at
0.7 V Swing
VHIGH
VLOW
VOX
Enable/Disable and Setup
Clock Stabilization from
Power-up
TSTABLE
Stopclock Set-up Time
TSS
Min
â
47
0.5
â
â
2
â
â
â35
45
â
â
0
0
0
0
â
1
â
â0.3
300
â
10.0
Typ Max Unit
â
250 ppm
â
53
%
â
4.0 V/ns
â
250
ps
â
350
ps
â VDD+0.3 V
â
0.8
V
â
35
uA
â
â
uA
â
55
%
â
50
ps
35
50
ps
40
108
ps
2
3.0
ps
2
3.1
ps
0.5
1.0
ps
â
100 ppm
â
8
V/ns
â
1.15
V
â
â
V
â
550 mV
â
1.8
ms
â
â
ns
Preliminary Rev. 0.1
5
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