SI52146 Datasheet, PDF (16/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 SIX OUTPUT CLOCK GENERATOR

Si52146
5. Pin Descriptions: 32-Pin QFN
Pin #
1
2
3
4
5
6
7
8
9
10
11
16
32 31 30 29 28 27 26 25
VDD 1
OE2¹ 2
SSON² 3
OE3¹ 4
OE4¹ 5
OE5¹ 6
NC 7
VDD 8
33
GND
24 VDD
23 DIFF5
22 DIFF5
21 VDD
20 DIFF4
19 DIFF4
18 DIFF3
17 DIFF3
9 10 11 12 13 14 15 16
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Table 7. Si52146 32-Pin QFN Descriptions
Name
VDD
OE2
SSON
OE3
OE4
OE5
NC
VDD
DIFF0
DIFF0
DIFF1
Type
PWR 3.3 V power supply
Description
I,PU 3.3 V input to disable DIFF2 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I, PD 3.3 V-tolerant input for enabling –0.5% spread on DIFF clocks
(internal 100 k pull-down)
I,PU 3.3 V input to disable DIFF3 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF4 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF5 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
NC No connect
PWR 3.3 V power supply
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
Preliminary Rev. 0.1