SI52146 Datasheet, PDF (19/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 SIX OUTPUT CLOCK GENERATOR

Si52146
7. Package Outline
Figure 6 illustrates the package details for the Si52146. Table 8 lists the values for the dimensions shown in the
illustration.
Figure 6. 32-Pin Quad Flat No Lead (QFN) Package
Table 8. Package Diagram Dimensions
Symbol
A
A1
A3
b
D
D2
e
E
E2
L
Min
0.70
0.00
0.175
0.20
4.90
3.15
4.90
3.15
0.30
Millimeters
Nom
0.75
0.02
0.20
0.25
5.00
3.20
0.50 BSC
5.00
3.20
0.40
Max
0.80
0.05
0.225
0.30
5.10
3.25
5.10
3.25
0.50
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
4. Coplanarity less than 0.08 mm.
5. Terminal #1 identifier and terminal numbering convention conform to
JESD 95-1 SPP-012.
Preliminary Rev. 0.1
19