SI52146 Datasheet, PDF (17/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 SIX OUTPUT CLOCK GENERATOR

Si52146
Pin #
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Table 7. Si52146 32-Pin QFN Descriptions
Name
DIFF1
VDD
DIFF2
DIFF2
VDD
DIFF3
DIFF3
DIFF4
DIFF4
VDD
DIFF5
DIFF5
VDD
SCLK
SDATA
CKPWRGD_PDB
VDD
XOUT
XIN/CLKIN
OE0
OE1
GND
Type
Description
O, DIF 0.7 V, 100 MHz differential clock
PWR 3.3 V power supply
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
PWR 3.3 V power supply
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
PWR 3.3 V power supply
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
PWR 3.3 V power supply
I SMBus compatible SCLOCK
I/O SMBus compatible SDATA
I, PU
PWR
3.3 V CMOS input. A real-time active low input for asserting power
down (PDB) and disabling all outputs (internal 100 k pull-up).
3.3 V power supply
O 25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input)
I 25.00 MHz crystal input or 3.3 V, 25 MHz clock input
I,PU 3.3 V input to disable DIFF0 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF1 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
GND Ground for bottom pad of the IC.
Preliminary Rev. 0.1
17