EFM8LB1 Datasheet, PDF (5/70 Pages) Silicon Laboratories – The EFM8LB1 device family are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below

3. System Overview
3.1 Introduction
EFM8LB1 Data Sheet
System Overview
C2CK/RSTb
C2D
Debug /
Programming
Hardware
Reset
Power-On
Reset
Supply
Monitor
CIP-51 8051 Controller
Core
64 KB ISP Flash
Program Memory
256 Byte SRAM
4096 Byte XRAM
VDD
VREGIN
GND
Power
Net
Voltage
Regulator
Independent
Watchdog
Timer
EXTCLK
XTAL1
XTAL2
System Clock
Configuration
Low Freq.
Oscillator
CMOS Clock
Input
External Crystal /
RC Oscillator
72 MHz 2%
Oscillator
24.5 MHz 2%
Oscillator
SYSCLK
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART0
UART1
Timers 0,
1, 2, 3, 4, 5
6-ch PCA
I2C Slave
Priority
Crossbar
Decoder
I2C /
SMBus
SPI
CRC
Config.
Logic
Units (4)
Crossbar
Control
Analog Peripherals
Internal
Reference
4 12-bit
DACs
VDD
VREF
14/12/10-
bit ADC
VDD
Temp
Sensor
+-+-
2 Comparators
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Figure 3.1. Detailed EFM8LB1 Block Diagram
VIO
P0.n
P1.n
P2.n
P3.n
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.4 | 4