EFM8LB1 Datasheet, PDF(16/70 Page) Silicon Laboratories – The EFM8LB1 device family are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below

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EFM8LB1 Datasheet, PDF (16/70 Pages) Silicon Laboratories – The EFM8LB1 device family are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below

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EFM8LB1 Data Sheet

Electrical Specifications

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

On-chip Precision Reference

IVREFP

ÂµA

Temperature Sensor

ITSENSE

120

Î¼A

Digital-to-Analog Converters

(DAC0, DAC1, DAC2, DAC3)6

IDAC

125

ÂµA

Comparators (CMP0, CMP1)

ICMP

CPMD = 11

CPMD = 10

0.5

Î¼A

CPMD = 01

Î¼A

CPMD = 00

Î¼A

Comparator Reference

ICPREF

TBD

Î¼A

Voltage Supply Monitor (VMON0) IVMON

Î¼A

Note:

1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increa-

ses supply current by the specified amount.

2. Includes supply current from internal LDO regulator, supply monitor, and High Frequency Oscillator.

3. Includes supply current from internal LDO regulator, supply monitor, and Low Frequency Oscillator.

4. ADC0 power excludes internal reference supply current.

5. The internal reference is enabled as-needed when operating the ADC in low power mode. Total ADC + Reference current will

depend on sampling rate.

6. DAC supply current for each enabled DA and not including external load on pin.

4.1.3 Reset and Supply Monitor

Table 4.3. Reset and Supply Monitor

Parameter

Symbol

VDD Supply Monitor Threshold

VVDDM

Power-On Reset (POR) Threshold VPOR

VDD Ramp Time

tRMP

Reset Delay from POR

tPOR

Reset Delay from non-POR source tRST

RST Low Time to Generate Reset tRSTL

Missing Clock Detector Response tMCD

Time (final rising edge to reset)

Missing Clock Detector Trigger

Frequency

FMCD

VDD Supply Monitor Turn-On Time tMON

Test Condition

Rising Voltage on VDD

Falling Voltage on VDD

Time to VDD > 2.2 V

Relative to VDD > VPOR

Time between release of reset

source and code execution

FSYSCLK >1 MHz

Min

Typ

Max

Unit

1.85

1.95

2.1

1.4

0.75

1.36

Î¼s

0.625

1.2

7.5

13.5

kHz

Î¼s

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