EFM8LB1 Datasheet, PDF (21/70 Pages) Silicon Laboratories – The EFM8LB1 device family are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below

EFM8LB1 Data Sheet
Electrical Specifications
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Power Supply Rejection Ratio
PSRR_ADC
—
TBD
—
dB
DC Performance
Integral Nonlinearity
INL
14 Bit Mode
-3.5⁴
-1.2 / +5
8.5⁴
LSB
12 Bit Mode
-1.9 -0.35 / +1
1.9
LSB
10 Bit Mode
-0.6
±0.2
0.6
LSB
Differential Nonlinearity (Guaran- DNL
teed Monotonic)
14 Bit Mode
12 Bit Mode
-1⁴
±1
2.5⁴
LSB
-0.9
±0.3
0.9
LSB
10 Bit Mode
-0.5
±0.2
0.5
LSB
Offset Error
E_OFF
14 Bit Mode
-8⁴
-2.5
8⁴
LSB
12 Bit Mode
-2
0
2
LSB
10 Bit Mode
-1
0
1
LSB
Offset Temperature Coefficient
TC_OFF
—
TBD
—
LSB/°C
Slope Error
E_M
14 Bit Mode
-15⁴
—
15⁴
LSB
12 Bit Mode
-2.5
—
2.5
LSB
10 Bit Mode
-1.1
—
1.1
LSB
Dynamic Performance 10 kHz Sine Wave Input 1 dB below full scale, Max throughput, using AGND pin
Signal-to-Noise
SNR
14 Bit Mode
66⁴
72
—
dB
12 Bit Mode
64
68
—
dB
10 Bit Mode
59
61
—
dB
Signal-to-Noise Plus Distortion
SNDR
14 Bit Mode
66⁴
72
—
dB
12 Bit Mode
64
68
—
dB
10 Bit Mode
59
61
—
dB
Total Harmonic Distortion (Up to
5th Harmonic)
THD
14 Bit Mode
12 Bit Mode
—
-74
—
dB
—
-72
—
dB
10 Bit Mode
—
-69
—
dB
Spurious-Free Dynamic Range
SFDR
14 Bit Mode
—
74
—
dB
12 Bit Mode
—
74
—
dB
10 Bit Mode
—
71
—
dB
Note:
1. This time is equivalent to four periods of a clock running at 18 MHz + 2%.
2. Conversion Time does not include Tracking Time. Total Conversion Time is:
Total Conversion Time = RPT × (ADTK + NUMBITS + 1) × T(SARCLK) + (T(ADCCLK) × 4)
where RPT is the number of conversions represented by the ADRPT field and ADCCLK is the clock selected for the ADC.
3. Absolute input pin voltage is limited by the V_IO supply.
4. Measured with characterization data and not production tested.
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.4 | 20